03:20 <bb-m-labs> build #369 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/369

03:49 <sb0> https://nixbld.m-labs.hk/build/124/log

07:55 <keesj> does litex not need a setup.py?

08:10 <_florent_> keesj: it's there: https://github.com/enjoy-digital/litex/blob/master/setup.py

08:16 <bb-m-labs> build #2452 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2452

08:20 <bb-m-labs> build #2928 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2928

08:21 <keesj> yea (it is) but it looks like https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L48 does not call it

08:22 <keesj> I don't know if the documentation (README) is "wrong" or the litex_setup.py

08:26 <keesj> [installing litex]...

08:26 <keesj> python3: can't open file 'setup.py': [Errno 2] No such file or directory

08:26 <keesj> (when running the script)

08:31 <rjo> sb0: i think the nucleo with the stm32f429 and ethernet is a good test platform for Thermostat. adamgreig will probably know more about it.

08:51 <rjo> sb0: i have only used the f103 and f446. my feeling is that there can be a lot of momentum in the existing embedded/rust/stm32/space/iot cross-sectional community.

11:54 <keesj> I am currently playing with this board http://blog.lambdaconcept.com/doku.php?id=products:lx16ddr and want to access the ddr3 and possibly also run bios (XIP) . I used litex_simple with the http://blog.lambdaconcept.com/doku.php?do=export_code&id=products:lx16ddr&codeblock=0 configuration but I am not getting anything on the serial

11:54 <keesj> (I also tried flashing the contents to flash)

11:56 <keesj> is there a published git repo I can use to validate my build/setup

13:00 <lkcl> sb0, whitequark: https://lists.librecores.org/pipermail/discussion/2019-February/000689.html

13:01 <lkcl> very experienced verilog developer (the author of many of the components released on opencores) is pointing out that nmigen using yosys which does casez instead of if-elif-elif-elif may be treated non-optimally for ASIC tape-out

13:01 <lkcl> except, i do not know enough to be able to answer or even know the subtleties of whether he is right

14:45 <_florent_> keesj: sorry haven't tested with this board. Have you tested with another board before? are you sure of your serial pins?

15:00 <keesj> yes the pins should be fine. I tested misoc on the papilio pro but never litex (neither papilio pro or the lx16ddr).

15:01 <keesj> I am also trying tinyfpga-bx but there the serial is defined differently / https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/tinyfpga_bx.py does not have the serial pins as part of the io but some magic "serial" at line 32 (so does the tinyfpga_b)

15:03 <keesj> I think I would like a bare-bones serial like blinky now just to test my platform(but there also I am getting stuked copying the whitequark UART https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/

15:03 <keesj> on tinyfpga-bx I am getting "litex.build.generic_platform.ConstraintError: Resource not found: serial:None"

15:04 <keesj> (I also hoocked a logic analyzer to see if perhaps the signal levels are wrong or similar but that looks fine).

15:31 <acathla> keesj, https://github.com/timvideos/litex-buildenv/blob/master/targets/tinyfpga_bx/base.py here you can see that the serial is added because the tinyfpga_bx can't use USB-serial yet.

15:32 <keesj> so perhaps I need to add the platform.add_extention thing.

15:33 <keesj> my board (and the tinyfpga indeed do not have a built-in fdti chip or similar) but I have plenty of such cables laying around.

15:33 <acathla> platform.add_extension(serial), yes

15:34 <acathla> It's 3.3V ! :)

15:35 <tinyfpga> keesj: I’m working getting the litex UART working through the built-in USB port...it’s not too bad!

15:35 <acathla> tinyfpga, yeah!

15:35 <tinyfpga> keesj, acathla: https://twitter.com/tinyfpga/status/1097704133774036992?s=21

15:38 <acathla> Cool. I just created my first basic CSR peripherals available through the serial-wishbone bridge

15:38 <keesj> I have have had a look at it (and will more when I have a little more time. as hobby I am creating a tinyfpga-bx clone based on up5k https://discourse.tinyfpga.com/t/tinyfpga-based-on-ice40-up5k-sg48/615 )

15:39 <keesj> I also looked at the migen usb parts but .. right now I first need to do something with DDR3

15:42 <tinyfpga> keesj, acathla: I’ve done just a little work with Migen and LiteX, but I’ve had a ton of fun doing it. After I get the USB UART working I want to get a HyperRAM interface working and a few other peripherals specific to my needs. It’s fun!

15:44 <keesj> ERROR: failed to place cell 'mem_1.1.0.0_RAM' of type 'ICESTORM_RAM' (is there the bx currently fails for me after adding the serial)

15:51 <acathla> How much RAM are you trying to use? You only have 16Kb I think

15:52 <acathla> 16KB*

16:44 <acathla> tinyfpga, how do you plug the hyperRAM to the tinyFPGA?

16:44 <tinyfpga> acathla: I’m working on a LiteX SoC for the TinyFPGA EX which has HyperRAM onboard

16:46 <tinyfpga> acathla: but you could make a simple shield or breakout board for a HyperRAM chip + TinyFPGA BX

16:47 <tinyfpga> acathla: or get a HyperRAM PMOD from esden

16:47 <acathla> simple... it's tiny BGA package only I suppose

16:50 <tinyfpga> acathla: the HyperRAM package is easy to reflow. If you’ve never done BGA reflow before, it’s the perfect one to start with. Oshpark can easily make PCBs that will work for HyperRAM.

16:51 <acathla> Ok. Why not, later. I still have plenty to learn first

22:51 <whitequark> lkcl: nmigen doesn't use casez. nmigen emits Yosys RTLIL, which does not have or need direct support for if/elif chains

22:53 <whitequark> lkcl: you can reply that while, for yosys, these two are exactly equivalent (they infer to the same priority encoder and this is guaranteed by yosys), if an external tool requires a specific kind of verilog, it would be trivial to modify nmigen to emit it