sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<lkcl> whitequark: appreciated, thank you.
<lkcl> btw would you have some time to look at what's being generated for the adder fpu nmigen? i'm a bit concerned by the excessive number of "BUF" entries in the graphviz (yosys "show" command)
<lkcl> on the original jondawson adder.v, the "show" command produces a graph that's a tall narrow stack
<whitequark> the BUF entries are a yosys abstraction
<whitequark> they do not affect the design at al
<whitequark> *all
<lkcl> ok cool.
<lkcl> i'm still marginally concerned, as there must be only around... a 10-deep set of dependencies
<lkcl> whereas the graph for the nmigen-generated verilog is... well... it's massive.
<whitequark> that's not really telling much
<lkcl> a chain possibly as high as 40 or 50 deep
<whitequark> I advise you to verify correctness functionally
<lkcl> ah it's correct :)
<whitequark> I don't generally bother looking at graphs or care about their shape
<whitequark> then I don't see the problem
<lkcl> ran about 500,000 unit tests
<whitequark> graphviz output is only really handy for artificial and reduced testcases
<lkcl> i'm concerned about gate count and chains, as this is for a low-power high speed processor
<whitequark> if it's the same logic it should synthesize to the same gates
<whitequark> now, nmigen is more prudent about resets, so this might be one difference
<lkcl> yeh i enabled "reset_less" on a number of signals where it's unnecessary to use them
<lkcl> unfortunately, i can see that's not helping, in some places, particularly registers
<whitequark> that sounds odd
<whitequark> if you reduce a case i can look at it
<lkcl> for example, there's a sticky bit which is a register in jondawson's original
<lkcl> (will give it a shot)
<lkcl> nmigen sets up a $next\sticky
<lkcl> which it resets to zero even though i said it should be reset_less
<whitequark> are you looking at synthesis results or not?
<whitequark> nmigen relies on an optimizing backend
<lkcl> i'm just generating verilog at the moment
<lkcl> there's a lot that i don't know i don't know, if you know what i mean :)
<lkcl> so, how would i get "synthesis results"?
<whitequark> synthesize it with yosys for your target
<whitequark> look at gate count
<lkcl> oh ok, got it.
<whitequark> $next stuff is completely transparent, it does not result in any logic being inferred
<lkcl> well, we haven't got that far, yet.
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<lkcl> ok. am going to experiment turning one of the classes into a Module.
<lkcl> appreciate the insights, whitequark.
<bb-m-labs> build #2453 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2453
<bb-m-labs> build #2929 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2929
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<bb-m-labs> build #2454 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2454
<bb-m-labs> build #2930 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2930
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<bb-m-labs> build #2455 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2455
<bb-m-labs> build #2931 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2931
<keesj> Hi
<keesj> I am still trying to get litex working on the lx16ddr board. I am now trying a modified lab003 https://github.com/enjoy-digital/fpga_101/tree/master/lab003 (e.g. a litex design without a CPU)
<keesj> and an UART Wishbone bridge
<keesj> oerpope
<keesj> perhaps this is related to https://pastebin.com/N2HtV87M
<keesj> (and perhaps also the CRG but I have validated that the reset itself does work)
<keesj> as test I am trying to read the DNA but the serial is dead.
<bb-m-labs> build #2456 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2456
<bb-m-labs> build #2932 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2932
<bb-m-labs> build #2457 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2457
<bb-m-labs> build #2933 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2933 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<acathla> keesj, you can easily grep the resulting verilog and the PCF file to be sure it's not missing anything
<keesj> I did a few more experiments (like combine wiht the blink example to see the clock is working and that the reset is also correct) , I remove the wishbone uart brige and replaced it with combinatory locig e.g. tx.eq(rx) and proved my serial is correcly echoing what I am typing.
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<travis-ci> m-labs/smoltcp#1210 (auto - a1d0e0c : Chris Branch): The build was broken.
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<sb0> whitequark: why are lit and outputcheck runtime dependencies of the conda package? is it just so buildbot installs them for running the tests?
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<whitequark> sb0: yeah
<bb-m-labs> build #2458 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2458
<bb-m-labs> build #2934 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2934
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