<lkcl>
btw would you have some time to look at what's being generated for the adder fpu nmigen? i'm a bit concerned by the excessive number of "BUF" entries in the graphviz (yosys "show" command)
<lkcl>
on the original jondawson adder.v, the "show" command produces a graph that's a tall narrow stack
<whitequark>
the BUF entries are a yosys abstraction
<whitequark>
they do not affect the design at al
<whitequark>
*all
<lkcl>
ok cool.
<lkcl>
i'm still marginally concerned, as there must be only around... a 10-deep set of dependencies
<lkcl>
whereas the graph for the nmigen-generated verilog is... well... it's massive.
<whitequark>
that's not really telling much
<lkcl>
a chain possibly as high as 40 or 50 deep
<whitequark>
I advise you to verify correctness functionally
<lkcl>
ah it's correct :)
<whitequark>
I don't generally bother looking at graphs or care about their shape
<whitequark>
then I don't see the problem
<lkcl>
ran about 500,000 unit tests
<whitequark>
graphviz output is only really handy for artificial and reduced testcases
<lkcl>
i'm concerned about gate count and chains, as this is for a low-power high speed processor
<whitequark>
if it's the same logic it should synthesize to the same gates
<whitequark>
now, nmigen is more prudent about resets, so this might be one difference
<lkcl>
yeh i enabled "reset_less" on a number of signals where it's unnecessary to use them
<lkcl>
unfortunately, i can see that's not helping, in some places, particularly registers
<whitequark>
that sounds odd
<whitequark>
if you reduce a case i can look at it
<lkcl>
for example, there's a sticky bit which is a register in jondawson's original
<lkcl>
(will give it a shot)
<lkcl>
nmigen sets up a $next\sticky
<lkcl>
which it resets to zero even though i said it should be reset_less
<whitequark>
are you looking at synthesis results or not?
<whitequark>
nmigen relies on an optimizing backend
<lkcl>
i'm just generating verilog at the moment
<lkcl>
there's a lot that i don't know i don't know, if you know what i mean :)
<lkcl>
so, how would i get "synthesis results"?
<whitequark>
synthesize it with yosys for your target
<whitequark>
look at gate count
<lkcl>
oh ok, got it.
<whitequark>
$next stuff is completely transparent, it does not result in any logic being inferred
<lkcl>
well, we haven't got that far, yet.
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<lkcl>
ok. am going to experiment turning one of the classes into a Module.
<acathla>
keesj, you can easily grep the resulting verilog and the PCF file to be sure it's not missing anything
<keesj>
I did a few more experiments (like combine wiht the blink example to see the clock is working and that the reset is also correct) , I remove the wishbone uart brige and replaced it with combinatory locig e.g. tx.eq(rx) and proved my serial is correcly echoing what I am typing.
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<travis-ci>
m-labs/smoltcp#1210 (auto - a1d0e0c : Chris Branch): The build was broken.