sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<bb-m-labs> build #2884 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2884 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<bb-m-labs> build #2371 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2371
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<bb-m-labs> build #2372 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2372
<bb-m-labs> build #1019 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/1019
<bb-m-labs> build #2885 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2885
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<keesj> what is the difference between adding a wishbone slave(address/size) and adding a memory region? (the two happen together most of the time but not always)
<keesj> and perhaps related.. what is csr :P
<keesj> I am speciflically looking at the 5 lines here https://github.com/m-labs/misoc/blob/master/misoc/targets/papilio_pro.py#L83
<key2_> what are you trying to o
<key2_> do
<key2_> CSR = config/status reg
<key2_> but if you don't know that, I guess you should first follow some tutorials ?
<keesj> well. overall the code "as" is doesn't really work for me for several reasons. if you have any links / pointers to tutorials for misoc that would be great but I think It won't directly solve my problems :P
<key2_> again, what are you trying to do
<keesj> I am trying to get a sane configuration for the papilio pro. the code as in git does not work. and when I fix one issue the next arrises hence my trying to understand a bit better if the problem is between keyboard and chair or the problem is in code.
<key2_> what's your error when you run this file
<keesj> perhaps it is more easy to do one step at the time. https://github.com/m-labs/misoc/blob/master/misoc/targets/papilio_pro.py#L73 configures cpu_reset_address to 0x6000 but the rom memory mapping in git is https://github.com/m-labs/misoc/blob/master/misoc/integration/soc_core.py#L15 0x0000 hence if I build "as is" the code won't boot
<keesj> I won't get any errors just a non booting system
<keesj> Next.. if I do configure boot from the bitstream (not spi) I need to modify the code e.g. replace the line 74 by adding rom_size (and this forces cpu_reset to 0)
<keesj> this will allo the rom code to boot but.. can't find flash and the bootflash command is missing from the bootloader (because the self.csr_devices.append("spiflash") is not added if we boot from rom)
<keesj> key2_: this is after I "fixed" the first that rom code was only allowed to start from 0 address
<keesj> key2_: can you suggest a tutorial? it would fancy adding tinyFPGA-BX as board
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<acathla> keesj, tinyFGPA_BX is supported by litex, I got it booting and running micropython (following a tutorial)
<acathla> Now I'm trying to understand how to add some hardware, a PWM for example, and how to control it from software.
<keesj> acathla: I Have that knowlegde in theory e.g. (the pwm/coding/wishbone ) from creating a wishbone can bus controller in vhdl. I started porting it to verilog, then wanted to look a migen and now generating socs
<keesj> but I like the low level stuff
<keesj> and from software on the pc or running on an embedded soc?
<acathla> I think i'll use a bridge instead of a slow CPU I don't need
<acathla> but I any information I can get =)
<keesj> I found that first learing simulation doing the "low level" pwm would be a good start before wrapping it all together. in the end pwm in verilog/vhdl is very simple hence it sould also in migen
<keesj> but if you don't go down deep it will remain vague.
<keesj> I am very new to migen but at least I have the rest of background (how cpu work , toolchains, linkers,assembly, hdl, python , git , serial etc etc etc).
<acathla> I already have a small project of motor control in migen, now I would like to use misoc/litex to not re-invent everything, like communication with a PC
<keesj> a cool, that sounds great.
<keesj> that said, I was looking at icestorm and also quite liked the serial-> led example https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/rs232demo.v (no cpu , no complexity, just a real bare bones uart RX driver and leds in 65 lines of code
<acathla> Hum, ok but verilog only, useless for me =)
<keesj> perhaps a nice challenge to generate that same code using migen?
<acathla> I already have a nice challenge : talk to the hardware CSR from software
<keesj> from deading the "bios" code, most stuff is just memory mapped but this is indeed where I need to first follow a tutorial e.g. I was looking at https://github.com/m-labs/misoc/blob/master/misoc/soaftware/bios/boot.c#L264
<acathla> 404.
<acathla> That's the problem, there is almost no documention or tutorial
<keesj> e.g. accessing memory at that flash boot address causes wishbone calls to the spi driver because it was mapped at that address
<keesj> (normally in c this unsigned int *flashbase is defineds as static unsigned int *flashbase to make sure the compiler actually does write to the memory when this is modified)
<keesj> the compiler else is allowed to make flashbase a local register and things tend to go wrong (e.g. the compiler can think this guys is stupid he is writing different things do the same address, let mee speed up and skip a few instructions)
<keesj> to me it look like the network driver also globally follows this pattern https://github.com/m-labs/misoc/blob/master/misoc/software/libnet/microudp.c#L118
<keesj> acathla: what tutorial did you follow ?
<acathla> It works but it does not help much to learn how it works
<acathla> I would like to replace micropython with baremetal C code, for the lm32, but I have no idea how to do that
<keesj> I was able to modify the bootloader e.g. bios.c. the next step (if you have access to SPI) is to write your own bare bones application. the code in bios.c (and linker scripts) is a good place to start.
<keesj> the first "challenge" if you don't want to hack the "bios" itself is to create an image that gets loaded by the bios. as you can see from the flashboot I posted earlier the image format is quite simple ,the load address is already hardcoded and what is storred in flash is "lenght,crc and the actuall data"
<keesj> "actual data" is the more complex thing to understand, you need to start with a normal piece of c code and compile it in such a way that the memory layour in the end matches the hardcoded load address and the image itself need to be a flat binary
<keesj> I don't know yet how this is done (did not find an example of this for litex/migen) but I am quite sure it exists .. still best guess for me now would be to first start with modifying the bios.c to get your hardware working . next focus on the "bare bones" loading asspect.
<keesj> to get something minimal working might look a bit like this code https://github.com/keesj/A13-OlinuXino-playground/tree/master/bare/versatile/07_cstartup but this was for arm not lm32 but the basics are the same (a little bit of assembly you can steal from the software/bios folder to inialize stack and such )
<keesj> a.. it looks like the basics are already documented here https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards (e.g. how to combine the bitstream and firmware)
<acathla> only micropython worked, gateware-flash failed even with last tinyprog version
<keesj> on that page there is a link called "bare Metal" but that part of the wiki is broken (also when I clone it)
<acathla> It's not broken it's empty i think
<keesj> but he is also saying, start by modifing the bios. it is quick and easy
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<sb0> whitequark: what's the appropriate yosys version for using nmigen?
<cr1901_modern> afaik, you need to be tracking git HEAD
<sb0> I just compiled the latest version (266511b29e) and there are still issues with signal names
<sb0> wire \$11 ; wire \$13 ; wire \$15 ; wire \$17 ; wire \$19 ; wire \$21 ; wire \$23 ;
<sb0> whitequark: I tried not to put a MultiReg into any m.submodules and did not get a warning
<key2_> sb0: what are you using nmigen for ?
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<sb0> default submodules names are also not so good (U0, U1, ...)
<sb0> key2_: making a small soc
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<acathla> keesj, it's almost all here too : https://github.com/timvideos/litex-buildenv/tree/master/gateware
<acathla> I successfully made a LED blink from the PC \o/
<acathla> But I cannot add a PWM to it, yet
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<whitequark> sb0: the signal names PR is not yet merged in yosys
<whitequark> clifford asked me to test it and i discovered that it's buggy on some verilog corner cases
<whitequark> (migen was buggy there, too)
<whitequark> e.g. verilog's ?: operator always zero-extends, even if both operands are signed and the context is signed
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<whitequark> as for the rest see https://github.com/m-labs/nmigen/issues
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<jason1> sb0, rjo: I successfully made kc705 flash and ping work with the latest artiq. Now I did the same procedure and used the same network settings, interface, switch for kc705 with the latest phaser built (and ARTIQ 3.7 with python 3.5). I can flash the device successfully. But I cannot ping. I tried ip addr show. The interface is up. The firewall is off. Note that this exact settings worked out to ping with the latest build.
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<jason1> arp and arp -a give no results. nmap -sP 192.168.0.0-255 just recognizes my interface ip address. Again this was the same network and setting that worked with kc705 with latest artiq build.
<jason1> The LED for ethernet cable is off on kc705. But it is on on all other ports (switch, interface).
<jason1> Correction: The 2 LEDs on kc705 (upper right and lower left) are on when I connect the ethernet cable. But the board's ip does not show up in nmap. I also tried to connect directly to my station with rj45. Still cannot ping the board.
<jason1> Can you help me to fix this please? rjo, sb0
<jason1> acathla
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<d_n|a> sb0: Regarding aiohttp, I can confirm that whatever you did or didn't prod, a recent version is pulled in now
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