01:36 <sb0> _florent_: the DDMTD system is only aligning SYSREF. the FPGA and DAC clocks are generated from the same oscillator and their phases are constant before the synchronization code runs

01:36 <sb0> and stay constant

01:37 <sb0> but before initialization, there are times when they are not, and times when they are not even derived from the same oscillator

06:51 <_florent_> sb0: i haven't looked closely at how DDMTD is working, but at the hmc7043 side, is abs(dac_sysref_phase - fpga_sysref_phase) almost constant for each boot? if not are you sure setup and hold is aligned only on the rising edge and not sometimes on the falling edge?

09:22 <sb0> _florent_: the coarse alignment code is looking at rising edges. https://github.com/m-labs/artiq/blob/master/artiq/gateware/jesd204_tools.py#L214

09:24 <sb0> _florent_: yes, the skew between the DAC and FPGA SYSREFs are constant. all we do to the HMC7043 is apply a constant analog delay to the DAC SYSREF, and use phase slips of 1 CLKIN period on all SYSREF channels

10:12 <acathla> https://wiki.f-si.org/index.php/FSiC2019

10:23 <key2_> acathla: interesting

10:24 <acathla> 2nd Free Silicon Conference 2019, in Paris

10:53 <keesj> how long until there is open hardware fpga silicon?

12:05 <bb-m-labs> build #2369 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2369

12:19 <bb-m-labs> build #2370 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2370