<fpgaminer>
hmmmmmmmmm for some reason this patched code doesn't actually _read_ anything from memory
<fpgaminer>
>8(
<fpgaminer>
And now Quartus is fscking up the hex file generated by elf-objcopy
<fpgaminer>
Hmmm ... Quartus is interpreting the addresses in the intel hex file as literal address of the altsyncram; so as 32-bit word addresses instead of byte addresses like elf-objcopy assumes
<fpgaminer>
Maybe I can write a script to fix this ...
<fpgaminer>
Great success!
<fpgaminer>
LM32 on Altera with the amazing blinking LED BIOS :D
<wolfspraul>
fpgaminer: lekernel needs to chime in on this, but I believe if you have clean patches that would make Milkymist (or parts of it) portable to Altera, without overly cluttering the codebase or Xilinx-support, we would love to merge it back into one unified codebase
<wolfspraul>
but I'm just saying this in general (or more asking/suggesting), without knowing the exact details of what you are currently porting and whether it makes sense to have one unified source base...
<wolfspraul>
I've heard from Sebastien before that even though our current focus is Xilinx and Spartan-6, when working on the Milkymist SoC he tried to stay away from Xilinx proprietary features to keep it an option to run Milkymist on Altera, by whoever and whenever, but to keep it a reachable goal
<wolfspraul>
rjeffries: sorry but it's so totally off I cannot even give specific feedback :-)
<wolfspraul>
900 EUR / mm2, MPW, 350/150nm, all wrong
<wolfspraul>
first we need an actual application (and sales forecast) where any other tech than what we are using now makes sense
<wolfspraul>
that won't be so easy to even get to
<wolfspraul>
at that point, a 6'' wafer costs about 150 USD
<wolfspraul>
the whole wafer, not a square mm
<wolfspraul>
below 500nm the fabs copyright gate-level design, so there's a big jump in 'prices' because you first need to understand what you actually pay for
<wolfspraul>
I have no idea why the lfoundry prices are so crazy high, one would need to talk with them to find out.
<wolfspraul>
there must a be a lot of services or IP in this, or it's just something they put up on the web, and their actual business is something else
<wolfspraul>
there are many foundries, I wouldn't be worried about it at this point at all
<wolfspraul>
lots and lots of lower hanging fruits imho
<wolfspraul>
you can check tsmc prices for older/bigger process nodes if you are interested
<wolfspraul>
but I see no application/need for us at all now
<rjeffries>
wolfspraul I wAS ONLY SHARING IMNFO sorry for caps
<wolfspraul>
maybe lfoundry is going after some very specific customers/markets (there are many details/differences in the fabrication process). I don't think they will just try to compete head-on with tsmc or even Chinese fabs. That'd be crazy. There's more to the story.
<wolfspraul>
rjeffries: yes sure, it's nice. It's a foundry in Germany, so it seems.
<wolfspraul>
but so what?
<rjeffries>
a modest size chip (less complex than MM) only costs $6k plus some cad time
<wolfspraul>
their prices are very high, like I said they must be going after some specific customers/markets
<wolfspraul>
which I don't understand
<wolfspraul>
is that 6k usd / piece ?
<rjeffries>
you may be right but they are set up for small runs so that is cvost effective
<wolfspraul>
is that 6k usd / piece ?
<rjeffries>
no $5K for a [roto run rgar priduces tens og packaged tested chips
<wolfspraul>
how many chips?
<rjeffries>
as I said tens of chips in [roto run. first of a few runs
<wolfspraul>
why tens of chips? how do you do the math?
<wolfspraul>
I understand they are doing MPW wafers, which I've only heard trouble from. But ok. for some specific customers who need high-end low-volume chips they have no other choice.
<rjeffries>
read what I wrote: this service is one where to reduce mask costs they place multiple projects on the same wafer
<wolfspraul>
rjeffries: why do you think it's "tens of chips"? how many?
<rjeffries>
wolfspraul I will go away. it doesn't matter when we are testing 1- 2- - 50 chips
<wolfspraul>
analog & mixed signal
<wolfspraul>
I am pretty sure they go after specific customers.
<wolfspraul>
from a very rough reading and thinking about their website
<wolfspraul>
rjeffries: go away?
<rjeffries>
they guys doing this are smart and are well awate of alternatives. I think you are comparing high volume alternatives
<wolfspraul>
just because we try to understand your comment about "low entry cost vendor"
<wolfspraul>
at least I am still reading your stuff...
<wolfspraul>
I think it's 1 chip for 6 k usd
<rjeffries>
I dislike you attitude I am not selling anything, I have some real world [priceing for a wafer that will start in 45 to 60 days.
<wolfspraul>
you dislike my attitude?
<wolfspraul>
ha ha
<wolfspraul>
6k / chip
<wolfspraul>
ron this is not a "low entry cost vendor"
<wolfspraul>
I think
<rjeffries>
wolfspraul read my lips: $5K is for the entire proto run, but excludes some CAD costs
<wolfspraul>
"entire proto run"?
<wolfspraul>
I think they are making individual wafers
<wolfspraul>
as per the schedule on that page
<wolfspraul>
and you can buy square millimeters on those wafers
<wolfspraul>
which is great
<wolfspraul>
some customers really want that
<wolfspraul>
very low volume, very high-end applications
<wolfspraul>
what does "entire proto run" mean?
<rjeffries>
I gyess you do not understand that for a small chip this can be cost effective. anyway i don't really care, please forget the whole thing
<wolfspraul>
why do you think you get "tens of chips" (how many?) for 6k usd?
<wolfspraul>
well it's either one chip, or tens of chips
<rjeffries>
wolf I do not yjink I LNOW becazuse yje group I am helping is doing this
<wolfspraul>
quite a big difference if you try to make an argument for "low entry cost vendor"
<rjeffries>
the $5k is indeed for the run. so either you believe or don't beleive.
<wolfspraul>
you pay per square millimeter, right?
<wolfspraul>
1 wafer
<wpwrak>
rjeffries: so that's with all the one-time costs. convert the CAD data, check it, make masks, etc.
<wolfspraul>
if you need 25 square mm, that's 25*650 EUR at the 350nm node
<wolfspraul>
oh sure
<wolfspraul>
there must be tons of services in this
<wolfspraul>
this looks like a very specialized fab
<wolfspraul>
they are going after very specific niche customers and markets (it looke like, GUESSING)
<rjeffries>
I am not the dircet person working with the fab.as I have stated the total cost is $5K plus some CAD charges which I do not know
<wolfspraul>
so that's 16,250 EUR / 25 mm2
<wolfspraul>
that gives you 1 chip for 16,250 EUR
<wolfspraul>
this is pretty normal in military applications
<wolfspraul>
and other high-end applications, satellites, etc.
<wpwrak>
wolfspraul: most of those services would have to be included anywhere. sending them machine-ready files would probably be quite difficult.
<wolfspraul>
wpwrak: no you can do that
<wolfspraul>
just completely different fabs and business models
<wolfspraul>
plus standardization needs time, so you are more likely to find such fabs on older tech
<rjeffries>
they test and pacake and turn in 4-6 weeks. I n3ed to learn aboiut that I think we hand off VHDL
<wolfspraul>
rjeffries: first try to find out whether it's 5k for one chip, or "tens of chips" :-)
<rjeffries>
when you are doing small chip the okder 159bn process node is not a big deal
<wpwrak>
wolfspraul: is the whole process 100% standardized ? or are there equipment/fab-specific variations ?
<wolfspraul>
wpwrak: there are definitely fabs that will take a mask from you in a 500nm process and just make your wafer without testing
<wolfspraul>
but then you need to know what you are doing, we are not ready for that either
<wolfspraul>
the older the tech, the more standardized
<wolfspraul>
I've heard below 500nm it will become fab-specific right now
<wpwrak>
wolfspraul: e.g., you couldn't just send a random panel to a PCB fab. it has to correspond to the board sizes they use (plus a few more parameters)
<rjeffries>
damn ity lisyen to me. for the 3rd time I KNOW repeat KNOW that that $5K is for teh group of 10-20 chips, period
<wolfspraul>
and then there are many variations/specialities in the production process, which some customers may need
<wolfspraul>
especialy in analog/mixed-signal chips which it seems lfoundry goes after
<wolfspraul>
rjeffries: 5k for 10-20 chips
<wolfspraul>
so they make multiple wafers?
<wpwrak>
rjeffries: i think wolfgang is a bit confused about the difference between your price and what they list on their site. but maybe they have volume discounts starting at 1 ;-)
<wolfspraul>
why do they give per square mm prices there?
<rjeffries>
wolfspraul the difference between you and the guys I am working with is they have a design ready to go (almost) and know other start-up that have used the same fab.
<wolfspraul>
great
<wolfspraul>
keep us posted :-)
<wolfspraul>
5k for 10-20 chips is possible, of course, but it's not on the url you gave us
<wolfspraul>
a 6'' wafer costs 150 USD
<wolfspraul>
or let's say 180
<rjeffries>
wolfspraul let's nor argue. you are ignoring things like a down economy and the joy of running a line fully booked
<wolfspraul>
so that's your bottom
<wolfspraul>
you are running your "full line" with mpw wafers? :-)
<wpwrak>
wolfspraul: as usual for small volumes, most of the cost is probably in the setup
<rjeffries>
please do not worrry about us. we'll do fine. have a great day
<rjeffries>
I do not run their plant. But I think I understand how the economics work. it is really cool when you are just starting to have a low barrier to entry. the VCs like that a lot
<wolfspraul>
rjeffries: are you or your guys customers of lfoundry.com ?
<rjeffries>
I am not teh guy working with LFoundry, as I already said. this apparently has zero interest, so let's not beat this poor dead horse.
<wolfspraul>
what kind of chip are you making?
<rjeffries>
My data is solid however. this process may not be what is needed for MM I dunno. the 150nm process node is old, 1999 but a gazillion chips are still fabbed using the old process
<wpwrak>
rjeffries: don't give up so quickly ;-) the information at the link you send says they're very expensive. then, the actual project you describe suggests they aren't. there's a mismatch of 1-2 orders of magnitude there. where does it come from ?
<rjeffries>
the fabs were paid for a long time ago I assume.
<wolfspraul>
old? no 150nm is very advanced
<rjeffries>
not reall
<wolfspraul>
plus there are huge differences between analog, mixed-signal and digital chips, and much variety in processing technology
<rjeffries>
65nm and below is advanced these days this is veryt old. wipipedia is your friend
<wolfspraul>
alright :-)
<rjeffries>
wpwrak yoiu guys amuse me. I guess you think I failed the IQ test. the prices I have mentioned are real,
<rjeffries>
so I don't care if people think it is bogus or not. in the real world price lists are just price lists.
<wpwrak>
rjeffries: you misunderstand. what we're curious about is what has to happen to get those cool prices. and not the way higher list prices.
<wpwrak>
rjeffries: kinda like buying airline tickets. there you can also pay for exactly the same service 10x the lowest price.
<rjeffries>
it i sthe down economy and the realitive lack of demand keeping a fab line full is similar to running an airline
<rjeffries>
taking off with empt seats is revenue lost forever
<rjeffries>
in  any case there is no funding for lekernel to create an asic for now, so this is a;; noise
<rjeffries>
s/a;;/all
<wpwrak>
rjeffries: alright, so the factor is the opportune moment. and your friends were lucky to be ready just in time.
<rjeffries>
not sure that is correct we have multiple fab runs planned.
<rjeffries>
these are 200mm wafers so when this is proven one wafer will result in a metric SHITLOAD of devices.
<wpwrak>
well, "just in time" may span a while. the economy doesn't reverse in a week. and they probably fixed the prices before starting. otherwise, there may be surprises ;-)
<wpwrak>
aaah, now we're talking
<wpwrak>
they promised a huge order. so that's where the money would be. the USD 5k run would just be a test.
<rjeffries>
the VCs are smart enough to factor that all in. not really there will be several tests actually
<rjeffries>
I am also pretty sure that list prices are a starting point for discussion in this business
<rjeffries>
I wonder what size lekernel estimates his SOC would be as an asic (area)
<wpwrak>
rjeffries: never assume other people are smart. never assume they're stupid. there may just be wildly different interpretations ;-)
<wolfspraul>
what is that chip (and the product the chip is in) doing?
<rjeffries>
great advice. ;) and challenging assumptions is fair. we shall see. maybe this first run really will cost a gazillion  dollars. ;)
<wpwrak>
naw, the first run will be cheap. it's the later runs that will cost :) it's not too different from how wolfgang got the ben made. his run size (1000 units) would normally be too small. but due to poor business, they agreed to take a 3k order in three chunks. (presumably with the understanding that later chunks may never happen, if the product doens't take off)
<wolfspraul>
wpwrak: in photolithography, the expensive thing is making the film, from what I understand so far
<wolfspraul>
a film can be used for 2-3k wafers
<rjeffries>
anything is possible. yup, and by sharing a wafer, that hight cost can be spread across multiple customers
<wolfspraul>
no wrong, sorry. film can be used for several years.
<wpwrak>
wolfspraul: so millions of wafers, if you want
<wolfspraul>
so what costs do we understand now? aside from not knowing much about process specialities in analog & mixed-signal
<wolfspraul>
1. wafer itself
<wolfspraul>
cheap
<wolfspraul>
4'' wafer 35 USD (according to azonenberg)
<wolfspraul>
6'' wafer 180 USD (what I was told in China)
<wpwrak>
that's just the raw material
<wolfspraul>
correct
<rjeffries>
these ar 8 inch wafers but who is counting (actually 200mm)
<wolfspraul>
yes that's for the pros
<wpwrak>
the machines and chemicals will cost a little, too ;-)
<wolfspraul>
then the film is expensive, making the film
<wolfspraul>
and the fab you are working with may see some of their IP in the making of that film
<wolfspraul>
i.e. you cannot take 'your' film out and to another fab
<rjeffries>
agree
<wolfspraul>
unless you agreed to that before, and/or you are on an older process tech, like 500nm or bigger
<wpwrak>
dunno how identical the fabs are. there may be many small variations that enter this
<wolfspraul>
once you have a film, let's assume the film is free and you can pick a fab just to go there with film, my understanding is runs are cheap too
<wolfspraul>
yes definitely, especially in <500nm, and analog/mixed-signal
<wpwrak>
even if they have the same machines, they may be in slightly different configurations
<wolfspraul>
yes
<wpwrak>
there's a reason why intel "clone" their fabs :)
<rjeffries>
I think the film (mask) is specific to the process, but I might be wrong.
<wolfspraul>
so but assuming the film is 'free', and we just pick a fab (i.e. we understand the process well enough to go to a new fab), then the making of the layers is also relatively cheap
<wpwrak>
a bit expensive, but i can understand their motivation very well ;-)
<wolfspraul>
relatively
<wolfspraul>
of course if you make more wafers, one-time costs can be shared among the wafers
<wolfspraul>
but even at 6'', 1 wafer can yield hundreds or thousands of chips, depending on chip size
<wolfspraul>
then there is testing, big problem
<rjeffries>
so where is this gouing? all chips can be $0 USD ?
<wolfspraul>
I currently understand very little/nothing about IC testing process, need to learn
<rjeffries>
running a fab is expensive due to tight clean room conditions
<wpwrak>
rjeffries: if you have the volume, almost :)
<wolfspraul>
I don't think so [clean-room]. there are many fabs, it's very competitive.
<wpwrak>
wolfspraul: testing probably adds quite a bit to the setup cost
<wolfspraul>
those investments are written off same as the photolithography and other equipment, over many years and many customers
<rjeffries>
a famous guy in semi industry said famously, maybe 15 or more years ago "all chips will cost $5 excpet for thos that cost less. "
<azonenberg_lab>
You guys talking fab?
<wpwrak>
;-))
<wolfspraul>
azonenberg_lab: hey, is that OK I used your ring oscillator assuming it was cc-by licensed or public domain?
<wpwrak>
azonenberg: is your alarm clock synced with IRC ? :)
<rjeffries>
not me. I entered this channel by mistake and stepped in horse poo up to my chin. ;)
<azonenberg_lab>
wpwrak: No, i saw the log on my other machine when i went to grab something
<azonenberg_lab>
This is my machine in the lab
<azonenberg_lab>
wolfspraul: I didnt explicitly pick license terms for it but cc-by is fine i guess
<wolfspraul>
excellent, thanks
<wolfspraul>
I always ask beforehand, this is a big exception.
<azonenberg_lab>
No worries
<wolfspraul>
I was in a rush to make those news and couldn't grab you.
<azonenberg_lab>
Be warned that it's never been tested or even analyzed
<azonenberg_lab>
So it might not quite be correct ;)
<rjeffries>
from the internets: My best friend ran off with my wife yesterday..... I really miss him
<wolfspraul>
azonenberg_lab: when someone makes an entire wafer full of ICs, how are they normally tested?
<wolfspraul>
is it tested when it's still a full wafer? or is it cut into pieces first, and then each chip is tested? or only after packaging?
<azonenberg_lab>
Basic testing for functionality, or failure analysis? Basic testing is a lot easier
<azonenberg_lab>
You design a probe card specific to that chip
<azonenberg_lab>
Its a ring-shaped PCB with a bunch of needles pointing into the hole at center
<wolfspraul>
ah wait, I took a video at Ingenic once, they were testing chips in fully packaged state
<azonenberg_lab>
The testing unit sticks that onto the bare wafer (before dicing) and checks each die
<azonenberg_lab>
The ones that fail are marked bad immediately
<azonenberg_lab>
Then they test again after dicing and packaging
<wolfspraul>
ok typical manufacturing, test after every step :-)
<azonenberg_lab>
But you are then more limited since you cant get to any of the test points unless they were brought out to pins
<wolfspraul>
sure, understood
<azonenberg_lab>
However, you can now test for packaging flaws
<azonenberg_lab>
So its still necessary
<wolfspraul>
you test along the whole way, every time for different failures and different reasons
<azonenberg_lab>
Yep
<azonenberg_lab>
Right now, for example, I am about to do visual inspection of an in-process die to see if my hardmask has pinholes in it
<wolfspraul>
how easy is it to take a photolithographic film from one fab to another?
<azonenberg_lab>
At least, once my hot plate gets warm enough that i can etch on it
<azonenberg_lab>
It depends a lot on the contents of the mask set
<azonenberg_lab>
If you licensed the fab's cell library you're locked into them
<azonenberg_lab>
If you used an in-house or open source cell lib (none of the fab's IP) then it's more feasible to move
<azonenberg_lab>
But you still might have to make some tweaks depending on process variaitons
<azonenberg_lab>
In my case, a consulting customer of mine has a MEMS device that was desigend completely in house
<azonenberg_lab>
and is now shopping fabs for price quotes
<azonenberg_lab>
to build a prototype
<azonenberg_lab>
However right now we just have the GDS (no physical masks), some little tweaks may be needed to adapt it to their specific process before making physical masks
<azonenberg_lab>
Even something as simple as switching from wet etching to lift-off means inverting the light/dark areas of the mask
<rjeffries>
have they checked LFoundry? I am aware of a MEMS start0up that uses the, (my project is not MEMS)
<wolfspraul>
I've heard that making physical masks is expensive, but then you can use them for several years. Is that correct?
<azonenberg_lab>
rjeffries: Not sure, i'm not involved in that
<azonenberg_lab>
I do simulation and wafer test
<azonenberg_lab>
plus a little bit of failure analysis here and there
<azonenberg_lab>
wolfspraul: They are definitely expensive to make
<azonenberg_lab>
How expensive, depends on the feature size and material
<azonenberg_lab>
for example really large masks can use film like PCBs
<azonenberg_lab>
Anything below like 15um feature size (on the mask) needs chrome on glass
<azonenberg_lab>
and really small feature sizes need even more exotic substrates
<azonenberg_lab>
Lifetime is pretty long
<wolfspraul>
ok
<azonenberg_lab>
they dont get physically damaged in any way unless something scratches them, they get dirty, etc
<wolfspraul>
confirms what I've learnt so far :-)
<azonenberg_lab>
woo my KOH is at 85C
<azonenberg_lab>
Time to take this die for a swim :)
<wolfspraul>
azonenberg_lab: how big are the manufacturing differences between digital, analog and mixed-signal ics?
<wolfspraul>
alright, we let you go off to more meaningful work :-)
<azonenberg_lab>
wolfspraul: I've only ever really done MEMS
<azonenberg_lab>
i'm learning digital stuff now
<azonenberg_lab>
and know zilch about analog - analog stuff scares me :P
<azonenberg_lab>
I joke that if a circuit i built has anything other than 0, 3.3, or 5 volts on a signal during normal operation, it's broken
<azonenberg_lab>
And I'll still be around - this is my living room fab lol
<azonenberg_lab>
So i IRC or write lab notes on the netbook while waiting for wafers to cook :p
<azonenberg_lab>
AFKs for a min to toss die in KOH
<azonenberg_lab>
back
<azonenberg_lab>
wolfspraul: Have you been following my home fab work at all?
<wolfspraul>
azonenberg_lab: yes definitely. but where is the best place to follow?
<azonenberg_lab>
#homecmos
<wolfspraul>
ah, great
<wpwrak>
azonenberg: how's the FOV coming along ? shopping for 12" wafers already ? :)
<azonenberg_lab>
i've been committing lab notes every day after i finish my experiments to the google code repo in the topic
<azonenberg_lab>
And when i said link, i meant let me know where you posted it :P
<azonenberg_lab>
As in, i'd like to hear what people think
<wolfspraul>
it takes some time for people to learn about your name, your project
<azonenberg_lab>
Yeah
<azonenberg_lab>
If you want to make your own renders, btw, i have Glade CAD files in the repo of it (and all of the standard cells i made to use in it)
<wolfspraul>
first time something new passes by, most likely we would dismiss it
<azonenberg_lab>
You can export them to GDS, DXF, or whatever
<wolfspraul>
you are too far ahead, but we get to it :-)
<azonenberg_lab>
Lol
<azonenberg_lab>
Well the CAD is way ahead of my fab capabilities atm
<wolfspraul>
for me first of all is about learning more, understanding where this could apply (for me)
<azonenberg_lab>
i'm still doing simple wet etching and am trying to get yields up
<wolfspraul>
my project is copyleft hardware, I believe there is a business model somewhere at the intersection between free software and manufacturing
<wolfspraul>
so I also wonder - how can some manufacturing technology, or the resulting chip/circuit/pcb, leverage free software in interesting ways to make a really good product...
<wolfspraul>
so from your homecmos to that, it's quite a way :-)
<azonenberg_lab>
Open source standard cell libraries
<azonenberg_lab>
And yes
<azonenberg_lab>
I do hope to be able t omake 4000 series chips or similar in the future (a year or so)
<wolfspraul>
exactly
<wolfspraul>
I know
<wolfspraul>
we will meet eventually :-)
<wolfspraul>
also it doesn't need to be a CPU, many interesting and powerful chips can be made
<azonenberg_lab>
Well yeah,  of course
<wolfspraul>
even with bigger/older processes
<azonenberg_lab>
But the educational value of making your own 7400 or 4000 series part
<azonenberg_lab>
From a blank wafer and a CAD program
<azonenberg_lab>
would be immense
<wolfspraul>
of course, excellent motivation and story
<wolfspraul>
cpu = heart
<azonenberg_lab>
lol, yes
<azonenberg_lab>
actually, this die literally has a heart :P
<azonenberg_lab>
It's a companion cube from Portal lol
<azonenberg_lab>
at 60 microns per pixel (large, i'm just testing the etch rates)
<lekernel>
wolfspraul, rjeffries: why don't you ask lfoundry for a quote for 1000 chips? then you'll know.
<lekernel>
azonenberg_lab, well, I guess you can print on A0 masks and a reprography machine with good optics to feed into the microscope :)
<lekernel>
so you avoid the expensive chrome on glass
<wolfspraul>
lekernel: I'm not going to ask lfoundry anything
<GitHub51>
[clang-lm32] sbourdeauducq pushed 51 new commits to master: http://bit.ly/mnvclJ
<GitHub51>
[clang-lm32/master] Allow comparison between block pointers and NULL pointer... - Douglas Gregor