#symbiflow on 2019-01-01 — irc logs at freenode.irclog.whitequark.org

09:36 <kraiskil> Is there a tutorial for end-users on how to get a 'hello world'-led blinker project done?

09:40 <daveshah> kraiskil: what FPGA family?

10:01 <digshadow> GuzTech: have you looked at the existing iob fuzzer?

10:01 <digshadow> Iirc there were some issues once multiple attributes are changed

10:05 <kraiskil> daveshah, Xilinx - I have a zybo

10:06 <kraiskil> why, are the flows that different?

10:06 <daveshah> Yes, in particular the current Xilinx flow is very experimental (I don't know much about it though)

10:17 <digshadow> I like the phrase experimental

11:09 <noopwafel> I assume I just pick the default options in the WebPACK installer? i.e. no DSP/SDK

11:14 <noopwafel> trying to clear up enough disk space reveals I have an existing full install of 2017.2, so that solves that

11:41 <GuzTech> digshadow: I did, but it seemed a bit confusing to me.

11:42 <GuzTech> Why does top.v use a 256-bit shift register connected to an IOB that has no output connected? Even though the KEEP attribute is there, it is still optimized away.

11:44 <GuzTech> My toplevel file just instantiates 1 OBUFT with a specific drive strength. No clock, no strobe, no shift register, just connect pin di to do using an OBUFT, and that gets me some diffs (strength 4, 8, 12, and 16 for LVCMOS33).

11:45 <GuzTech> The IOB fuzzer seems incomplete, so I looked at the lutinit one which should be simple enough, and after diffing, segmaker is used but I couldn't quite figure out how to get that working or what it does exactly.

11:45 <GuzTech> Then again, I didn't spend that much time on it (begin new year's eve and all).

11:45 <GuzTech> Happy new year peeps!

12:26 <noopwafel> digshadow: so artix7 is GTP (explains why no GTX) -> the primitives are GTP_CHANNEL_n. they look fun. am going to need more coffee.

12:27 <digshadow> noopwafel: yeah that sounds about right...I think I mentioned I don't remember the details of the IO options on 7 series

12:27 <digshadow> noopwafel: let me know if you need help to get started

12:31 <digshadow> White is whitelogger multiplying

12:33 <digshadow> why is

14:10 <dbe_> Anyone alive?

14:12 <sorear> it’s new year’s day

14:34 <digshadow> dbe_: going to run the turing test on us?

14:41 <dbe_> hi guys, I was just curious if someone is here. I saw some very interesting talks on the 35c3 and would like to help with the project.

14:43 <digshadow> dbe_: did a specific part of the project catch your interest?

14:44 <digshadow> noopwafel: you are probably past this now, but default installation is fine

14:45 <dbe_> I would like to work on the bitstreams for altera devices (as a distant goal), but should probably begin with writing tests, documentation and some light python coding

14:48 <digshadow> dbe_: do you have a specific interest in altera? Have you used their devices a lot?

14:50 <dbe_> I've dabbled some with altera CPLDs and FPGAs (all low cost ones) and have access to some altera evaluation boards. Well and I liked the Quartus Software much more than the Xilinx-counterpart

14:53 <digshadow> mithro: we have a mailing list right? trying to find it

14:53 <mithro> Yes

14:53 <digshadow> going to e-mail MMCM guy, I have a thought on one of the behaviors we saw

14:54 <mithro> https://lists.librecores.org/listinfo

14:54 <tpb> Title: lists.librecores.org Mailing Lists (at lists.librecores.org)

14:54 <digshadow> ah? there is a prjxray specific list

14:57 <digshadow> dbe_: there is an altera FPGA project by rqou. I'm not sure the current state of it though: https://github.com/rqou/project-chibi

14:57 <tpb> Title: GitHub - rqou/project-chibi (at github.com)

14:57 <digshadow> or CPLD maybe?

14:57 <digshadow> yeah Altera Max V CPLD

14:58 <digshadow> dbe_: what Xilinx software did you use? ISE or Vivado? IMHO Vivdado is much nicer than ISE

15:00 <dbe_> digshadow: I think I used both. I switched to a more powerful PC so maybe it's an non-issue now. And as I said, I'm not narrowly interested in only altera related work, especially in the beginning.

15:01 <digshadow> dbe_: I would encourage you to work with an existing project if that also interests you. We are still trying to get critical mass on a lot of these parts

15:02 <digshadow> Good options would be Xilinx 7 series (contact me or mithro) or Lattice ECP5 work (contact daveshah)

15:03 <dbe_> oh, what about the 2070(?) project? I didn't find it on the website but mithro told us, that that project would be a good startingpoint for beginners

15:03 <digshadow> These both have significant momentum behind them...not just at the bitstream level, but also related synthesis and PnR

15:03 <mithro> dbe_: You mean the xc2064?

15:03 <dbe_> or yeah

15:03 <dbe_> oh

15:03 <digshadow> dbe_: oh yeah, project 2064. Thats sort of a hobby project of mine (and Ken S as well)

15:04 <digshadow> We have a lot of docs from Ken now that need to be crunched on

15:04 <digshadow> Although less directly applicable than the others, it would be a good demo project to help people understand the process

15:05 <digshadow> I also know someone interested in understanding some apple 2 peripherals, so there is a cool factor there

15:05 <dbe_> digshadow: what are the requirements to work on the docs from ken?

15:05 <digshadow> (or maybe amiga...need to check)

15:05 <digshadow> dbe_: I'd like to see a bitstream disassembler, ideally bitstream to verilog

15:05 <digshadow> mithro: are those docs public?

15:05 <digshadow> I have a copy, I can ask ken if I can give them out

15:06 <mithro> dbe_: The bitstream is pretty well understood

15:06 <inquisitiv3> Is Symbiflow a temporary name, or are it going to be kept?

15:06 <mithro> https://github.com/shirriff/xc2064

15:06 <tpb> Title: GitHub - shirriff/xc2064: Reverse engineering the XC2064 FPGA (at github.com)

15:07 <mithro> inquisitiv3: we might do a rebrand sometime this year depending on a couple of things - why?

15:07 <digshadow> mithro: theres more than that

15:07 <digshadow> there was google doc with a bunch of complimentary info I think?

15:09 <mithro> digshadow: Not sure how relevant that information is?

15:09 <mithro> cr1901_modern started working on Verilog simulation models

15:10 <digshadow> mithro: do you believe ken's docs are complete?

15:10 <digshadow> in the github repo

15:10 <mithro> https://github.com/cr1901/symbiflow-arch-defs/tree/xc20xx/xc20xx/primitives

15:10 <tpb> Title: symbiflow-arch-defs/xc20xx/primitives at xc20xx · cr1901/symbiflow-arch-defs · GitHub (at github.com)

15:10 <digshadow> hmm had not seen cr1901s repo there

15:12 <inquisitiv3> mithro: I saw that symbiflow.io and symbiflow.org was free, so I wondered if noone had bothered to purchase the domain or of there's going to be a rebranding.

15:26 <dbe_> mithro: I heard you are the guy to talk to when one would like to contribute to the project. Is there any work for a beginner left to do on the Xilinx 7 series part of the project?

15:26 <mithro> dbe_: Yes! Still heaps to do, depending on what you are "beginner" at

15:30 <mithro> dbe_: If you know Python already, there is *heaps* you can do

15:30 <dbe_> mithro: well I'm an EE with some python experience (mostly data acquisition and analysis) and have a tiny bit of experience using myhdl+Quartus. I wanted to check out nMigen next but was distracted by your 35c3 talk. I could also help with testing and documentation, but as a non-native speaker my English is meh

15:34 <inquisitiv3> mithro: Btw, I would like to thank you for your talk at CCC. It was great!

15:35 <mithro> inquisitiv3: Thanks!

15:35 <inquisitiv3> I didn't understand most of it, but it got me interested in FPGAs