02:41 <Ayana> hello

02:43 <Ayana> i got some job for fuzzing xadc in 35c3 but i got a bug in processing make

02:44 <perillamint> https://pastebin.com/eLHJRv9z

02:44 <tpb> Title: Traceback (most recent call last): File "/home/ayana/prjxray/fuzzers/033-mon- - Pastebin.com (at pastebin.com)

02:44 <perillamint> While running XADC fuzzer, fuzzer failed to fuzz specimen 008

02:46 <perillamint> Does anyone know how we can resolve this error?

04:04 <OmniMancer> What software is actually required to be installed to attempt to target a xilinx series 7 FPGA with open source tools?

04:11 <sorear> it is not currently possible to target a series 7 with open source tools only

04:11 <sorear> there are a couple flows which use yosys in conjunction with ise or vivado

04:15 <OmniMancer> There is some work ongoing for open place and route for artix 7?

04:28 <sorear> yes

04:28 <sorear> it WILL BE possible to use an entirely open flow

12:19 <OmniMancer> How may one help with Artix 7 documentation work?

12:20 <sorear> documentation is mostly done, we need people to write place and route tools

12:21 <OmniMancer> Ah

12:50 <OmniMancer> Is there anything where small incremental contribution is possible?

12:55 <sorear> uh, some other people here have long lists of those

13:08 <OmniMancer> Ah, I shall hang around in here tomorrow then

17:47 <litghost> perillamint: That means none of the tags found a solution. Are you sure that ADC configuration bits were being toggled? Are you sure that tilegrid.json has a definition for the XADC tile?

17:50 <litghost> OmniMancer: Depends on what you want to focus on. Right now there is work in BRAM, MMCM, IOB and XADC documentation. There is also a need to expand base addresses in tilegrid to include all tiles found in parts (python and tcl skills recommended). On the place and route side, there are not architectural models for MMCM, IOB or XADC (python, xml and C++ skills recommended). There is also a need to write tests for both

17:50 <litghost> prjxray and symbiflow

22:20 <whatnick> ping daveshah, working out openocd profile for the LFE5U-25F

22:20 <daveshah> hiya

22:20 <daveshah> Best is to look for an existing profile for the fleafpga

22:21 <sorear> OmniMancer: litghost replied, check https://logs.timvideos.us/%23symbiflow/latest.log.html near [17:57]

22:21 <daveshah> The fleafpga uses a less common FTDI chip, iirc

22:21 <OmniMancer> Thanks sorear

22:21 <OmniMancer> daveshah: do you have any idea how different ECP3 series is from ECP5?

22:22 <daveshah> By no means identical

22:22 <daveshah> I had a quick look at a bitstream once and I remember a few commands at least being different

22:23 <daveshah> Logic tiles look a bit different in terms of routing too

22:30 <whatnick> daveshah: we identified it from the schematic

22:32 <whatnick> It has a FT230XQ for USB serial/JTAG

22:32 <nats`> hey plop guyz :)

22:43 <whatnick> hey nats`

22:43 <whatnick> i am just getting back into IRC land ..

22:43 <whatnick> been too long in twitter oceans

22:43 <whatnick> working on ECP5 FleaFpga

22:43 <whatnick> Hopefully will have picorv soc on it soon ...

22:43 <sorear> welcome!

22:47 <daveshah> whatnick: so you'll need to first see if openocd supports that chip

22:48 <daveshah> If it does, you'll need to create a config file with the correct pinout