<tpb>
Title: Parallel build does not build all the targets · Issue #568 · SymbiFlow/prjxray · GitHub (at github.com)
<whatnick>
mithro: which host board are you using for Xray fuzzing ? Looking at setting up the fuzzer , since I have the headless xilinix toolchain already.
<litghost>
If you re-run make at the fuzzer root?
<litghost>
whatnick: Fuzzing only requires vivado
<mithro>
whatnick: You don't really use a "board" for X-Ray
<litghost>
It's purely software
<mithro>
whatnick: If you want to *use* the toolchain to produce bitstreams for designs that is a totally different thing
<whatnick>
I have the headless toolchain set-up and taking space on my machine. Planning to put it to good use if possible.
<whatnick>
If it is to bitstream only and back analysis of that I can keep running that ...
<whatnick>
Is the input vhdl manually generated ? auto-generated by the fuzzer ?
<mithro>
whatnick: No VHDL involved here - do you mean Verilog?
<whatnick>
Again my lack of knowledge there .... off to read fuzzer flow ...
<whatnick>
Help out with mapping the xilinix board and get off the proprietary toolchain I have the Mimas board. From your talk it is mostly usable ?
<mithro>
whatnick: Most of the Mimas boards are Spartan 6 based. Do you have a Mimas A7 or an older Mimas / Mimas V2?
<whatnick>
I did the fupy build for it using the prop toolchain over pycon 2018, aiming to get x-ray to the point where I can do the same with OS chain. I have the V2
<mithro>
whatnick: The V2 is a Spartan 6 based board. The Spartan 6 it is not supported by Project X-Ray or SymbiFlow at all
<whatnick>
Aaahh ...
<whatnick>
okay time to get a new board ..
<mithro>
whatnick: SymbiFlow is also not ready for doing FuPy stuff on any Xilinx board yet either
<mithro>
whatnick: Yosys+nextpnr works fine with FuPy on the iCE40 parts
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<whatnick>
I only have the flea for ecp5 and an ice40 stick ..
<whatnick>
stepping back the overall goal is to do high speed ADC + Maths on FPGA to capture instantenous AC power usage and appliance finger printing ...
<whatnick>
It does not have to support Fupy, but will make it easier to iterate ...
<whatnick>
I have some ice40 parts + ADC as well from Olimex ..
<whatnick>
Pulled the lpf file from the manufacturer sample
<whatnick>
Will need to make other relevant changes to account for 25F in makefile I assume, as well as openocd
<whatnick>
This "../../misc/basecfgs/empty_lfe5um5g-45f.config --textcfg $@ --um5g-45k" targets 45f
<mithro>
whatnick: Getting ECP5 stuff into the TimVideos LiteX-BuildEnv would be super cool, but again the #timvideos IRC channel would be the best place for that
<mithro>
litghost: Any idea what is going on with the artix7/tile_type_BRAM_L.json file?
<mithro>
kgugala: Do you have any idea about the parallel make issue?
<OmniMancer>
What is the most reasonable way to install that version of Vivado?
<mithro>
OmniMancer: Download it from the Xilinx website and install it?
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<kgugala>
mithro: TBH I'm starting to suspect a make bug - there seems to be some kind a race condition between the targets generated with fuzzer macro
<kgugala>
*some kind of a race condition
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<kgugala>
I have random results in each run
<mithro>
I think we should make the output of the fuzzers more readable / less verbose so you can better understand what is actually going on
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<kgugala>
it is visible what is going on - some fuzzers were newer run
<kgugala>
no matter the fact that they are in the makefile
<kgugala>
for some reason make decided that those should not be run
<kgugala>
the missing part of the DB is because some fuzzer didn't have a chance to produce it
<kgugala>
this is why I suspect make itself
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<sxpert>
what would be the proper command lines to generate a basic design from a simple .v file
<mithro>
kgugala: Do you know how to run make in debug mode?
<mithro>
sxpert: Hrm? If your asking how to create a bitstream from a simple verilog file for an ice40 I recommend asking in the #yosys or ##openfpga channels
<sxpert>
ok
* sxpert
heads there
<kgugala>
mithro: yes, I know
<kgugala>
I'll check what is happening there
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