<sorear>
wish we could reserve DRAM for efforts to document the ecp5 DQSDLL blocks and whatever Xilinx has, and come up with a different term like Async RAM or LUT RAM for that thing
<sorear>
probably too late
<sorear>
maybe DisRAM
<sorear>
yes, distributed RAM versus external DDRx RAM
<mithro>
tmichalak: To generate images -> do cd ~/github/SymbiFlow/symbiflow-arch-defs/build/artix7/primitives/slicel then type "make <tab>"
<daveshah>
I don't think anyone ever uses DRAM for DQS primitives etc?
<mithro>
tmichalak: You'll get something like "make file__home_tansell_github_SymbiFlow_symbiflow-arch-defs_artix7_primitives_slicel_slicel.bb.svg"
<daveshah>
If nothing else that SDRAM doesn't need them
<mithro>
sorear: I almost always say DDR RAM
<daveshah>
What would be confusing is an FPGA with built in DRAM
<mithro>
daveshah: inbuilt DDR RAM? :-P
<daveshah>
ie the Anlogic parts with die stack SDRAM
<mithro>
daveshah: The two ram types in iCE40UP5K is alway confusing :-P
<daveshah>
Pretty sure I've seen a FPGA with DDR2 in package
<sorear>
xilinx and altera have talked a lot about HBM/HMC for high end parts but idk if anything ever shipped
<sorear>
but re. DRAM I'm thinking more litedram and the overwhelming external computer industry context
<sorear>
it seems like a better fit for gain cells (2T/3T using "parasitic" gate capacitance of a dedicated read transistor) than traditional 1T1C DRAM
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<mithro>
tmichalak: You want to add this alias to your ~/.bash_aliases or ~/.bash_rc
<mithro>
alias cdb='cd $(pwd | sed -e"s,$(git rev-parse --show-toplevel),$(git rev-parse --show-toplevel)/build," -e"s,build/build,,")'
<mithro>
lets you quickly switch between the build and non-build at the same directory level
<mithro>
tmichalak: So it looks like the stuff in the dram directory just tests to check that VPR can place and route those primitives