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<mithro> Morning!
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<sf-slack2> <kgugala> Morning
<sf-slack2> <pgielda> Afternoon ;)
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<mithro> kgugla: How goes the bel timing import?
<sf-slack2> <kgugala> @mithro: I just pushed common timings merge, so now, the last step - use those in the code I implemented for arch-defs
<sf-slack2> <kgugala> the merge is a part of this PR https://github.com/SymbiFlow/prjxray/pull/706
<tpb> Title: fuzzers: timings: add bel timing fuzzer by kgugala · Pull Request #706 · SymbiFlow/prjxray · GitHub (at github.com)
<sf-slack2> <kgugala> for merging I needed the emit functionality of python-sdf-timing
<sf-slack2> <kgugala> which was implemented over the easter weekend (+ fixed a lot of bugs in the sdf-timing lib)
<kgugala> there is also v2x issue with arrays of modules (listed here https://github.com/SymbiFlow/symbiflow-arch-defs/issues/595)
<tpb> Title: v2x features to replace XML generation · Issue #595 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<kgugala> IMO, this would have to be fixed before we can migrate from hand written xmls to the generated from verilog ones
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<mithro> Looks like clifford is adding specify support to Yosys -> https://github.com/YosysHQ/yosys/pull/946
<tpb> Title: Add specify parser by cliffordwolf · Pull Request #946 · YosysHQ/yosys · GitHub (at github.com)
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<JuanP> Hello, in page https://symbiflow.github.io/prjtrellis-db/ECP5/tilehtml/PLC2.html, I don't get the meaning of E1_H02W0501 and the 1s in the F0B2 and F2B2. Are the latter some descriptive bits? Thanks
<JuanP> I don't get the bigger picture of this
<daveshah> E1_H02W0501 -> wire H02W0501 one to the east
<daveshah> F0B2 -> frame 0 bit 2
<daveshah> The 1s in F0B2, etc are the bits set to enable that connection
<daveshah> I explain a bit here: https://youtu.be/cTOkgDZli_o
<JuanP> Thanks you Dave. I spent the whole we to review the code of Yosys, NextPNR and trellis. This is the only thing I wasn't really sure about
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<hackerfoo> Does anyone know why RAM64M is commented out in xc7/techmap/cells_map.v?
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<mithro> hackerfoo: So I think you want to get the "echo" files produce when running the test
<hackerfoo> For which test? I don't see any for RAM64M.
<hackerfoo> mithro: ^
<mithro> hackerfoo: It is a bit confusing to me why the DRAM128_DP pack-pattern is on both the DPO and SPO direct thingies...
<mithro> There should be a prepack file which has the molecules in it...
<hackerfoo> Thanks, I found it.
<mithro> hackerfoo: There is an interesting comment at the top of dpram128.pb_type.xml -> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/primitives/slicem/Ndram/dpram128.pb_type.xml#L1-L7
<tpb> Title: symbiflow-arch-defs/dpram128.pb_type.xml at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro> hackerfoo: It also looks like some of those comments might be wrong....
<hackerfoo> Yeah...
<mithro> hackerfoo: I think that pack-pattern is suppose to join two 128 bit LUT rams together into a molecule so that WAUSED is correctly set...
<mithro> hackerfoo: The other pack patterns in this file seem to be called DRAM128 and DRAM128_D...
<hackerfoo> I don't see DPRAM128 in the diagram for RAM128X1D, or anywhere else in the CLB user guide. Aren't we using the same names as in the guide?
<tpb> Title: Add stubs for RAMs. · SymbiFlow/symbiflow-arch-defs@e5a282f · GitHub (at github.com)
<tpb> Title: Add stubs for RAMs. · SymbiFlow/symbiflow-arch-defs@e5a282f · GitHub (at github.com)
<hackerfoo> I think I need to read more before I can make sense out of this.
<hackerfoo> I'm looking at slicem.pb_type.xml, but I can't see what's out of place yet.
<mithro> hackerfoo: What does the molecule echo file show?
<tpb> Title: pre_packing_molecules_and_patterns.echo · GitHub (at gist.github.com)
<mithro> hackerfoo: The important one is that last molecule;
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> hackerfoo: pack-patterns have two usages -- they are either for
<mithro> (a) carry chains
<hackerfoo> Okay, I'm not sure what ram0.stub is, but that seems problematic?
<mithro> (b) Combining small parts into large parts which should be grouped together
<tpb> Title: Architecture Reference Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io)
<hackerfoo> Thanks
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<mithro> hackerfoo: It is unclear to me why a pack-pattern of f7a_mux stub f7b_mux makes sense...
<mithro> hackerfoo: it is also unclear to me why someone would name something just "stub"
<hackerfoo> mithro: Yeah. I'll look into that and see where it's coming from.
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<hackerfoo> It looks like those lines in the commit, but I'm not sure what it should be. I'll try reverting them and see what I get.
<hackerfoo> The stub is to group the DRAMs: "To ensure that all DRAMs are co-located within a SLICE, this block is a simple passthrough black box to allow a pack pattern for dual port DRAMs."
<hackerfoo> But I'm not sure where ram0.stub is coming from. Maybe it gets eliminated later? It's just 2 wires of output = input.
<tpb> Title: yosys/abc.box at xc7mux · YosysHQ/yosys · GitHub (at github.com)
<tpb> Title: yosys/abc.lut at xc7mux · YosysHQ/yosys · GitHub (at github.com)
<tpb> Title: symbiflow-arch-defs/cells_map.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
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<tpb> Title: FASM on iCE40 - Google Docs (at docs.google.com)
<tpb> Title: SymbiFlow iCE40 Verilog to Routing Status - Google Docs (at docs.google.com)
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<tpb> Title: Rename distributed ram (DRAM) to LUT ram · Issue #616 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro> hackerfoo1: Are you going to log an issue about the naming and stuff?
<hackerfoo1> Yes, I am.
<mithro> okay great
<mithro> Will add my 2 cents after you finish
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<tpb> Title: {S,D}PRAM128 name is misleading and not in the CLB User Guide · Issue #617 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)