<digshadow>
FWIW I almost exclusively dealt with bit definitions. If you have a routing question, I'm probably not the person to ask
<digshadow>
Also timing
<digshadow>
Ex: if you have questions about RAM32X1S bitstream encoding I can provide insight there
<hackerfoo>
Well, is this what you expect? The data input line goes to DI2, and the data output to O6.
<digshadow>
hackerfoo: looking at the user guide, two observations. First, the DI naming is very confusing with net DID[0] => pin DID2, net DID[1] => pint DID1. That aside, it notes in a few things (ex: "Figure 2-11: 64 X 3 Simple Dual Port Distributed RAM (RAM64M)") that they go to pin DI1 when only one is used
<digshadow>
If its unclear though, I'd probably make a minitest with a number of configurations (or using existing minitests) and take a look at the routing in the various configurations
<digshadow>
Let me see whats in the minitests dir...
<digshadow>
Yeah if you synthesize prjxray/fuzzers/018-clb-ram/minitest, maybe modifying it to use the commented out top module
<digshadow>
you should get a bunch of different examples
<digshadow>
nvm no modification needed, just synthesize it
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<hackerfoo>
digshadow: Thanks. I'll look at it a little later if I can.
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<tpb>
Title: Make v2x produce the new composable interconnect specification again (IE Revert #637). · Issue #642 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<tpb>
Title: ice40: Adding real world timing values. · mithro/symbiflow-arch-defs@4c996d5 · GitHub (at github.com)
<sf-slack2>
<acomodi> mithro: regarding https://github.com/SymbiFlow/symbiflow-arch-defs/issues/642, all the golden pb_types/model should be in the `new` format, am I correct? Than the `xmlsort.xsl` handles the translation to the `old` format to have the interconnects compatible with current VPR
<sf-slack2>
<acomodi> mithro: ok, got it, I'll revert the PR then
<sf-slack2>
<kgugala> @mithro In parallel I'm working on bel timings import into arch.xml. There I switched from handwritten xmls to the ones generated from verilog (I discussed that with @elms and @litghost). Now, with v2x handling multiple instances I should be able to finish this
<sf-slack2>
<kgugala> @mithro but if we switch to a new interconnect generation, wouldn't it break the flow?
<sf-slack2>
<kgugala> can vpr handle the new interconnect format?
<mithro>
kgugala: See what acomodi said -- The `xmlsort.xsl` handles the translation to the `old` format to have the interconnects compatible with current VPR
<mithro>
kgugala: Which is done as part of the architecture merging step
<sf-slack2>
<kgugala> oh
<sf-slack2>
<kgugala> OK
<sf-slack2>
<kgugala> I must have missed that
<mithro>
kgugala: VPR doesn't handle <xi:include> either
<sf-slack2>
<tmichalak> kokoro seems to be stuck, force-run tag doesn't work, anyone else experiences this problem? I wonder if there is anything else I can do except wait...
<sf-slack2>
<mkurc> @tmichalak I made a PR to arch-defs an hour ago and the kokoro seems to be still running. I don't know if I can see logs of a pending build.
<sf-slack2>
<tmichalak> @mkurc: maybe the problem only applies to new runs only, let me know if your run finishes
<sf-slack2>
<acomodi> Could it be due to the fact that there are multiple PRs that are being run on kokoro?
<sf-slack2>
<tmichalak> @acomodi: actually I start to think that it is indeed the case
<sf-slack2>
<acomodi> for instance I opened a PR as well a half an hour ago
<sf-slack2>
<mkurc> Might be so. It would be nice to have a interface to see load of the build server.
<sf-slack2>
<tmichalak> @acomodi: I noticed that when running multiple PRs for fuzzers stabilization there were some hickups in kokoro's runs
<sf-slack2>
<tmichalak> @mkurc: I agree
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<sf-slack2>
<mkurc> @tmichalak Kokoro finished checking my PR successfully
<sf-slack2>
<tmichalak> @mkurc: okay thanks, so I have 2 PRs running, i.e. one running and the second one about to run with the use of the force-run tag. Unfortunately, nothing changes for 2 hours now.
<sf-slack2>
<acomodi> There is no way right now to run only one of the different checks right? (e.g. XC7-presubmit failed and I want to re-run only that one)
<sf-slack2>
<kgugala> I don't think so
<sf-slack2>
<kgugala> just rerun all of them
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<sf-slack2>
<acomodi> update on equivalent tiles: I have update the PR https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/36. Now the placer can swap the blocks in equivalent tiles as well. CI still fails as the arch files do not include the tiles tag.
<tpb>
Title: Sign in to GitHub · GitHub (at github.com)
<sf-slack2>
<acomodi> By running the `ff_ce_sr` tests I got into a fasm2frames issue
<sf-slack2>
<acomodi> `prjxray.fasm_assembler.FasmInconsistentBits: FASM line "CLBLM_R_X5Y117.SLICEL_X1.DOUTMUX.O5" wanted to clear bit (131743, 35, 21) but was set by FASM line "CLBLM_R_X5Y117.SLICEL_X1.DOUTMUX.D5Q"`
<sf-slack2>
<acomodi> the tests that work right now are: `chain_packing`, `simple_ff` and `buttons`
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<hackerfoo>
I was reading through the CLB user guide last night that the software is responsible for setting A6 high in 32 bit RAM modes to keep O5/O6 independent.
<hackerfoo>
I also made VPR use O5 and got a different alternating pattern.
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<sf-slack2>
<acomodi> `counter` also is working
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<hackerfoo>
Does anyone have a partial reconfiguration license for Vivado? Any plans for SymbiFlow to do partial reconfiguration?