<elms>
mgieda: looks like livereload target will run the last catch all `sphinx-build -M livereload` does that do something meaningful? (Out of touch with Sphinx)
<elms>
mgielda: ^^
<sf-slack2>
<mgielda> $ sphinx-build -M livereload . _build/ Running Sphinx v1.7.6 Sphinx error: Builder name livereload not registered or available through entry point
<sf-slack2>
<kgugala> and vpr fails on missing interconnect
<sf-slack2>
<kgugala> Am I missing something?
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<sf-slack2>
<mkurc> @kgugala The first thing I see is that there is no `blif_model=".subckt MUXF6"` in the pb_type tag in the one generated from verilog.
<sf-slack2>
<kgugala> yes, I know that
<sf-slack2>
<kgugala> is that causing the troubles?
<sf-slack2>
<mkurc> I guess that without it the VPR will not know that it should use the pb_type for MUXF6 from the eblif file.
<sf-slack2>
<mkurc> There is a statement that for a "primitive only" pb_type the blif_model is required
<sf-slack2>
<kgugala> OK blif_model there solves the case
<sf-slack2>
<acomodi> if I am not wrong, VPR expects an `interconnect` tag as well which is not optional. If it is not present in the pb_type.xml it will fail (I think it could be empty though: `<interconnect/>`)
<sf-slack2>
<kgugala> it does not fail when blif_model is set
<sf-slack2>
<mkurc> I guess that the primitive pb_types do not need interconnect as there is nothing inside. They are just empty shells with pins which reference BLIF models. Though it is not stated explicitly in the documentation (at least I haven't found it).
<sf-slack2>
<acomodi> Yeah, that makes sense
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<litghost>
Primitive pb_types are required to not have interconnect
<litghost>
And primitive pb_types are identified by their use of the blif_model property
<tpb>
Title: Improve timing model support for 7-series · Issue #293 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack2>
<mkurc> @litghost There is an attribute called "ptc" in the "graph_node" table. What is it used for ?
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<sf-slack2>
<kgugala> @elms thanks
<sf-slack2>
<kgugala> Those asterisks in PLL's do look like spec violation
<litghost>
mkurc: It is overloaded, but for CHANX and CHANY it is to assign visual locations in the VPR renderer. ptc's are handled automatically via the channels2 code
<tpb>
Title: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack2>
<acomodi> litghost: I can take a look on that and fix all. I will probably squash all the commits in chunks to make thinks clearer
<litghost>
acomodi: Agreed, sounds good
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<hackerfoo>
I got it to finish without errors by ripping out the UART and ERROR_OUTPUT_LOGIC in ram_test.v.
<hackerfoo>
Although it generated a bad line in the TCL script: set_property FIXED_ROUTE [list ] $net
<hackerfoo>
So I commented that out. I'm going to see if I can fix it.
<tpb>
Title: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<tpb>
Title: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack2>
<acomodi> in that PR, which is now closed, was stated that the `direct` connections should change from `<direct input="XXXX.CLOCK_ENABLE" output="in_cen.EN" name="XXXX">` to `<direct><port name="CLOCK_ENABLE" type="input"/> <port name="EN" type="output" from="in_cen"/></direct>`
<tpb>
Title: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro>
Well yosys now passes the slicel.sim.v model!
<litghost>
yay
<sf-slack2>
<acomodi> Yep, should I leave the things as they are right now (input and output are not in separate tags) then?
<mithro>
but netlistsvg fails on the constants...
<litghost>
In addition the new syntax I don't believe handles arrays of modules
<litghost>
acomodi: Leave the direct connects as they are
<mithro>
litghost: Where does CARRY0_CONST goes where?
<litghost>
root of the chain
<litghost>
in the SLICE
<litghost>
Just look at the XML
<mithro>
litghost: Oh, I see why muxgen isn't used as much anymore
<mithro>
litghost: Also, it seems PRECYINIT_MUX just connects AX to CI_INIT ?
<litghost>
litghost: Ya, C0 and C1 are now handled in synthesis
<litghost>
mithro: And treated as parameters, rather than routed
<litghost>
mithro: I could add them back as constant sources in the pb_type, but I'm following the principle, if you can do it in synthesis, do that
<sf-slack2>
<acomodi> litghost, mithro: I have checked the status of the v2x PR (https://github.com/SymbiFlow/symbiflow-arch-defs/pull/316) I have noticed that some v2x tests will fail if some assertions are not commented out. I guess that when we have green travis we should merge the PR and then work on solving the issues to the tool.
<tpb>
Title: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost>
acomodi: Let's get a green CI on merge, and put commented out tests in an issue with a fix list
<sf-slack2>
<acomodi> litghost: how to automatic reformat in arch-defs? I got this in travis CI https://pastebin.com/4CWkkjnv
<tpb>
Title: Scanning dependencies of target check_python yapf needs to reformat /home/travi - Pastebin.com (at pastebin.com)
<litghost>
make format_python
<sf-slack2>
<acomodi> right, thanks
<mithro>
litghost: I think we should add `make format` which runs `make format_python` and the others...
<litghost>
mithro: Sure
<litghost>
mithro: I believe elms was working on a PR to format other types that does that
<sf-slack2>
<acomodi> i got some files which are not related to v2x formatted as well
<sf-slack2>
<acomodi> should i just add them as well in your opinion?
<litghost>
acomodi: That is a side affect of a yapf change
<mithro>
acomodi: Check your yapf version -- see pull request for litghost
<litghost>
acomodi: Merge with master
<mithro>
be back in 30m
<sf-slack2>
<acomodi> Ok
<sf-slack2>
<acomodi> litghost: now `testarch presubmit` completes successfully on CI, I expect the same to happen for the others. I've pushed format corrections and hopefully CI will be green on everything
<tpb>
Title: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<tpb>
Title: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost>
acomodi: Assuming CI is green, please address the remaining PR comments. They are pretty small
<sf-slack2>
<acomodi> So, actually for the time being I have disabled the whole `tests` directory
<sf-slack2>
<acomodi> Yep, I am on it
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<litghost>
acomodi: Why tests? It was working on the previous master?
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<litghost>
Ah, you mean utils/vlog/tests
<litghost>
Not tests
<sf-slack2>
<acomodi> yep, sorry utils/vlog/tests
<sf-slack2>
<acomodi> they have been added with #316 PR. I suggest that for now we wait for green CI and merge. And think about its solution afterwards. I have opened a ticket for that already. I'll solve the other changes to be done not related to the vlog tests and I think it could be good to go
<mithro>
Back now
<hackerfoo>
Is there a way to feed a clock signal into clk during simulation in Vivado? Or should I generate my own clock.
<mithro>
hackerfoo: I think you have to generate your own
<mithro>
hackerfoo: Maybe ask on ##openfpga?
<sf-slack2>
<acomodi> litghost: done, ice40 previously failed, but it was for an http issue while downloading conda
<litghost>
hackerfoo: I usually just force it
<litghost>
hackerfoo: Right click the clk and then "Force clock ..."
<mithro>
litghost: Is there a way we can make cmake symlink the files into the build directory?
<mithro>
litghost: So they should be copied into the build directory?
<litghost>
mithro: Can you reprahse?
<mithro>
litghost: I have an autolinter running on my editor, if I open a file in xc7/primitives/... it gets all angry about missing includes (for the auto-generated files). If I open it in build/xc7/primitives/.. it gets overwritten every build...
<litghost>
mithro: Yes
<litghost>
mithro: What's the question?
<mithro>
litghost: If it was a symlink instead then I could open it in build/xc7/xxx and but it would actually be changing the xc7/xxx file...
<litghost>
mithro: Yes, but it would only work on linux
<litghost>
Well I guess you have to look carefully, the pb_type name is CARRY0, the subckt is CARRY0_CONST
<mithro>
litghost: Oh - I see what is going on, the carry0.sim.v isn't in the CMakelists.txt file...
<litghost>
mithro: And isn't used
<hackerfoo>
I tried removing all connections to O5 in the model and pb_type for dpram32, but ram_test still doesn't work on hardware. So that isn't the problem. It must just be the routing, but I can't find a good way to check that things are routed properly.
<hackerfoo>
I think I might just route everthing to switches and lights on the board.
<litghost>
hackerfoo: That's what the test in xc7/tests/dram does
<litghost>
hackerfoo: And how I debugged RAM64X1D to begin with
<hackerfoo>
I wish I had just stuck with that from the start. Maybe. If I can figure it out that way.