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<sorear>
The ecp5 and 7series projects assume extending vpr instead of arachne; there’s also some evidence the Altera toolchain is or at one point was a vpr derivative
<balrog>
sorear: the Xilinx license agreement contains abc
<balrog>
"abc version 01104p"
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<rqou>
the altera toolchain is definitely vpr
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<rqou>
tiered mac tables? i.e. a mac table in external ram with cache in front? :P
<sorear>
156Mpps?
<sorear>
Seems like a lot…?
<azonenberg>
sorear: the actual number is a bit lower
<azonenberg>
but roughly 2 Mpps per 1G port and 20 Mpps per 10G port
<azonenberg>
if all maxed out at full line rate
<azonenberg>
with min sized packets
<azonenberg>
24x 1G and 4x 10G
<azonenberg>
i forget the exact number but it was somewhere between 1 and 2 clocks per packet at 156.25 MHz which is what i plan to run the fabric at (10 Gbps / 32 bit data path)
<sorear>
10g/64 you mean
<awygle>
azonenberg: yeah I was thinking of the queues. Mac table is large but not really relevant to total usage.
<awygle>
Also the Cyclone can do DDR3 on every pin, or something like that
<azonenberg>
awygle: again latency
<azonenberg>
dram makes little sense for something like this
<azonenberg>
sorear: oops yeah
<azonenberg>
sorry my tcp offload engine right now runs at a 64-bit datapath
<azonenberg>
at a 32 bit*
<azonenberg>
at 312.5 MHz
<azonenberg>
awygle: re queues, the sizes i made up were totally arbitrary
<azonenberg>
they mgiht grow/shrink by a factor of 4 or so
<azonenberg>
or more
<azonenberg>
I'm going to go do some simulations and see
<mithro>
Well - just need to get the clocks going
<azonenberg>
basically just run a discrete event simulation for N packets with various flow distributions
<azonenberg>
And see what happens
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<awygle>
Sure. But queues are substantially less latency sensitive and so more amenable to external memory interfacing.
<azonenberg>
sooo
<azonenberg>
think about the throguhput required
<azonenberg>
in order to be able to keep all output ports fed
<azonenberg>
You need to be able to pop from the queues at 24*1 + 4*10 = 24+40 = 64 Gbps
<awygle>
Like I said, I did zero math on this lol
<azonenberg>
I'm doing the math right now in front of you, to see if my gut feeling is right
<azonenberg>
64 Gbps is roughly the raw bandwidth, before addressing/activation/refresh overhead
<azonenberg>
of an entire SODIMM of DDR3 1066
<azonenberg>
And that's just for the pops, you need that much again for pushes
<azonenberg>
Adding in overhead, you're looking at probably two SODIMMs of DDR3 1333 - 1600
<azonenberg>
With maybe 1 MB of actual memory used by your queues
<awygle>
checks out
<azonenberg>
Meanwhile, if you went with a fast SRAM, like QDR-II+
<azonenberg>
They're normally 36 bits wide, round to 32 assuming we use a few for metadata of some sort, simple dual port
<azonenberg>
Say 1 Gbps data rate
<azonenberg>
So two of them would be enough to do 64 Gbps writes and 64 Gbps reads
<azonenberg>
still doesnt seem to make sense
<azonenberg>
I *do* plan to stick a single QDR-II+ on my brain card, just in case (for future feature expansion) but it would be for smaller things like routing tables/ACLs
<azonenberg>
Since you won't be reading/writing a full MTU worth of data each packet, the required bandwidth should be less and the several MB of low-latency capacity would be worth it
<azonenberg>
anyway i'm writing up a simulator now to model queueing behavior and see if my gut feeling of required fifo sizes is even remotely right
<awygle>
just looked up QDR-IV. It is crazy fast lol
<awygle>
Probably $$$ tho
<azonenberg>
QDR-IV uses POD signaling iirc like DDR4
<azonenberg>
Which most low cost FPGAs dont support
<azonenberg>
QDR-II+ is SSTL
<azonenberg>
like DDRx
<azonenberg>
also if your IOBs can't keep up no point in having faster ram
* sorear
would describe the MAC issue as “ops/s”, not “latency”, a highish latency but pipelined memory would be fine
<azonenberg>
awygle: My initial plan was to have zero qos
<Marex>
rqou: there were those switchboxes with some 6 bits, but only two were always set
<azonenberg>
and say, when a packet arrives if there's no buffer space, drop it
<azonenberg>
whatever's in the queue keeps moving
<azonenberg>
But i guess we could look into qos too
<awygle>
azonenberg: i don't actually care what the design is, i just want it specified
<awygle>
i'm fine with "drop incoming if full"
<azonenberg>
ah ok
<rqou>
Marex: btw i did see the academic paper explaining how stratix interconnect was designed, but it doesn't have detailed connectivity
<rqou>
does the patent?
<azonenberg>
The way i see it, this should be a pretty rare occurrence
<azonenberg>
With the flow patterns i will have in my network at least
<azonenberg>
awygle: also, i'm considering a hybrid queue architecture
<azonenberg>
you have a small block ram fifo dedicated to each exit port
<azonenberg>
When that fills up you start pushing data into the QDR
<azonenberg>
There is not enough QDR bandwidth for all ports to keep up, but as long as overflows of the small queues are relatively infrequent the QDR can cover some overflows
<azonenberg>
in particular, the QDR has approximately half the bandwidth needed for the entire switch fabric's exit queues
<awygle>
yes, that seems sane to me
<azonenberg>
So basically use block ram to keep the bandwidth high, then spill to QDR as needed
<awygle>
you're much more likely to get "one port is getting spammed"
<azonenberg>
the actual exit queues will contain descriptors of some sort
<azonenberg>
that point to either their local bram or the qdr
<azonenberg>
Then you pop from the appropriate source
<awygle>
actually that's a good point. what's the worst imbalance you could _actually_ have?
<azonenberg>
Worst theoretically possible?
<awygle>
you can't actually overflow all the exit queues at once
<azonenberg>
23x 1G + 4x 10G ports
<awygle>
because there's not enough ingress
<azonenberg>
sending to a single 1G port
<azonenberg>
So 63 Gbps -> 1 Gbps
<azonenberg>
oh, hmm... i see what you're saying
<azonenberg>
i dont know what the worst case setup is
<azonenberg>
but i do know that the exit queue bandwidth, for full line rate forwarding everywhere, has to be 64 Gbps
<awygle>
i guess this is only actually relevant to the DDR discussion from last night, since QDR is full duplex
<azonenberg>
yes its perfect for fifos etc
<awygle>
anyway, just something to think about.
<azonenberg>
I'm planning to throw a 72 Mbit x36 QDR-II+ on the board (instead of the 36 i had originally planned)
<azonenberg>
you can populate either but this will give more flexibility and its not THAT expensive
<azonenberg>
ok its a $250 sram but compared to the whole project :p
<azonenberg>
72 Mbits into 28 ports is an average of 2.57 Mb/port of buffer but it'll be shared so you can have much more buffer if not all ports are spammed at once
<azonenberg>
awygle: also, i just found the worst case scenario
<azonenberg>
Every 1G port sends to the adjacent 1G port at full line rate
<azonenberg>
Every 10G port sends to the adjacent 10G port at full line rate
<azonenberg>
Except one 1G port
<azonenberg>
Which is sending 1/28 Gbps to every port
<azonenberg>
So every port is 35 Mbps over capacity, all the time
<azonenberg>
except that one
<shapr>
which project is this? MOTHERSHIP ?
<azonenberg>
shapr: LATENTRED
<shapr>
ah, ok
<azonenberg>
1G x24 / 10G x4 ethernet switch
<azonenberg>
1U top of rack
<sorear>
What was the diff with orange again?
<shapr>
Is your name generator code public?
<azonenberg>
shapr: i use online random word generators and iterate a few times until it sounds good
<shapr>
ah, ok
<azonenberg>
then sometimes tweak a bit to make a "family" name
<azonenberg>
i pulled LATENT out of a random word gen and it suggested some other color
<azonenberg>
So i decided the family code name is LATENTPACKET, the first project is LATENTRED, second is LATENTORANGE, etc
<shapr>
all related to LATENTPACKET ?
<azonenberg>
sorear: LATENTORANGE will be a core switch with 10G/40G interfaces
<azonenberg>
shapr: LATENTPACKET is the umbrella project for all of my open source fpga-based networking gear
<shapr>
neat
<rqou>
wait Marex are cyclone 1..4 all very similar?
<rqou>
what about 5?
<whitequark>
I thought the entire cyclone series is mostly just die shrinks?
<rqou>
and here edmund was calling this project useless
<rqou>
whitequark: no, it did pick up some arch changes
<balrog>
I believe 3->4 was a die shrink
<balrog>
to the point where the JTAG IDs are the same
<balrog>
but others were arch changes too
<balrog>
Marex: I forget, are you working on Cyclone RE?
<rqou>
they were at one point
<awygle>
iirc Cyclone 10 LP is like... Arria V?
<awygle>
or maybe just Cyclone 10 generally
<rqou>
is arria the mid-range part?
<awygle>
yeah
<rqou>
what is max10 forked off of?
<awygle>
it's the Kintex, approximately
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<rqou>
it seems interesting to me that altera has bits packed much more nicely than xilinx
<sorear>
Is there a page somewhere with a chart of what all these names refer to?
<rqou>
xilinx control bits are even more all over the place
<rqou>
what names?
<rqou>
LAB/LE/CLB/slice/tile/etc.?
<rqou>
or branding names?
<sorear>
All Altera and Xilinx product names
<rqou>
somebody should make one :P
<shapr>
hackaday mentioned that m.2 card with a xilinx 7 series on it ... an artix? I think
<shapr>
and I had the same question sorear just had
<shapr>
I have an unused m.2 slot in my laptop for a WWAN card, could be interesting
<rqou>
current xilinx naming from lowest-end to highest-end is spartan, artix, kintex, virtex
<rqou>
starting from "7 series"
<shapr>
too bad they're not alphabetical or otherwise sensible
<rqou>
the successor series are "ultrascale" and "ultrascale+"
<shapr>
those are post- 7 series?
<rqou>
before 7-series there was only spartan and virtex
<shapr>
does that make ultrascale 8 series, or is it the levels above virtex?
<rqou>
before that there were just XCxxxx numbers afaik
<rqou>
ultrascale isn't called 8 series because the architecture is still very similar
<balrog>
isn't ultrascale parallel to 7 series?
<awygle>
ultrascale is "eight series" and ultrascale plus is "nine series" but they're barely different, primarily a smaller process and some multi-die stuff iirc
<rqou>
"smaller process" <-- i guess you can say that
<rqou>
afaik the ultrascale is finfet
<awygle>
aren't the US+es 10nm or 7nm?
<sorear>
At one point I thought ultra scale was defined by being multi SLR, but no
<balrog>
US+ is 16nm right?
<balrog>
and US is 20nm
<rqou>
no, that's different
<shapr>
sounds like this reference card is desperately needed
<Marex>
balrog: was
<rqou>
multi-SLR exists in 7-series too afaik
<Marex>
rqou: the patent does
<rqou>
and only certain parts
<rqou>
Marex: link?
<awygle>
oh these are all bigger than i thought. 7 series is 28nm, US is 20nm, US+ is 16nm FinFET.
<sorear>
I’m pretty sure I’ve heard of both spartan 6 and 3
<balrog>
btw, why the jump from 3 to 6 series?
<kc8apf>
Xilinx series #s track the virtex line
<awygle>
there are 4s and 5s but only Virtex iirc
<balrog>
ah, right
<kc8apf>
Spartan is the value-line and only gets updated occasionally
<shapr>
virtex is the mass production line?
<kc8apf>
there was much surprise at spartan-7
<kc8apf>
virtex was the high-perf line
<balrog>
kc8apf: was there? it took a few years to show up
<balrog>
(and a ton of whining)
<shapr>
who do I bribe to write up this reference card?
<rqou>
btw afaik various people have fully(???) re'd s6 but just didn't write any comprehensible documentation
<shapr>
yeah, but that's inside azonenberg's personal account, is there not a github org?
<rqou>
maybe someone should clean that up? (*hint* *hint*)
<awygle>
azonenberg: ^^
<shapr>
azonenberg: feel like creating a github org for openfpga?
<kc8apf>
I've put all my gaffe projects under gaffe-logic
<kc8apf>
was planning to buy a domain for it soon as well
<shapr>
doesn't github support custom names now?
<shapr>
I have several personal DNS names, I should try that.
<kc8apf>
I'm OK with using it for general FPGA info
<kc8apf>
shapr: yes, they do
<shapr>
awygle: I probably don't have a chunk of spare time before Thursday
* shapr
learns more Go
<awygle>
how has your experience with Go been?
<rqou>
my opinion is still "I don't really see the point of go"
<awygle>
what i think the point of go is depends on how much sleep i've had the night before
<awygle>
on good days it's "python but faster" on bad days it's "google's attempt to further commoditize software development, see also Java"
<kc8apf>
Go is rpike getting frustrated with C
<whitequark>
and not learning a single thing about programming since the 70s
<kc8apf>
exactly
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<rqou>
I'd much rather have go-esque channels in rust
<kc8apf>
can't you do that with a crate?
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<whitequark>
there are go-esque channels in rust
<rqou>
yeah i figured there would be
<rqou>
i just haven't needed it yet
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<kc8apf>
practically everything in Rust supports Send
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<awygle>
it's been fascinating to watch rust sprint towards async web stuff. just another case of "my use case is not the typical use case" i guess
<awygle>
somehow the ergonomics discussion got completely dominated by Futures for a long time
<qu1j0t3>
whitequark | and not learning a single thing about programming since the 70s |||| YEPPPPP
<kc8apf>
I just smile and nod while everyone creates the new "fastest, bestest Rust HTTP server evar!"
<kc8apf>
I want better auto-docs for structs used as bitfields
<awygle>
i wanted failure, i'm not sure what i want now
<awygle>
an excuse to write more rust, i guess
<shapr>
awygle: I don't much like Go so far
<awygle>
oh no i want the stdlib portability refactoring
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<shapr>
My primary language for personal projects is Haskell, if that says anything.
<shapr>
I would enjoy a job writing Rust
<awygle>
shapr: yeah i thought you were a Functional Type, so i was curious how go was treating you
<shapr>
in my opinion, one of the goals of pure FP is reducing cognitive load
<awygle>
i want the stdlib portability refactoring followed by a blog post on "here is how to port std to a new platform"
<shapr>
seems to me Go has the same goal, but it does that by cutting the language down to tinker toys.
<kc8apf>
I know of one company hiring for Rust
<shapr>
I know a bunch hiring for Rust, and others for Haskell.
<shapr>
I don't understand why Go chose to use explicit loops instead of at a minimum "for item in collection"
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<shapr>
My first day writing Go I discovered there's no tool to detect variable shadowing. You can't find this: https://goplay.space/#f-iLyFTvGzJ
<awygle>
My minimum bar for non indexed loops is for (key, value) in dictionary
<awygle>
Which a depressingly small number of languages make work
<shapr>
Go feels very hacked together
<kc8apf>
and Rust just found another bug for me by asserting on signed underflow
<shapr>
I'm used to being able to write "swap (a,b) = (b,a)" in Haskell, or "lambda (a,b): (b,a)" in Python, but that doesn't work in Go
<shapr>
though a coworker pointed out that works fine if you do it inline in Go code
<shapr>
The system collections are type-safe generic, but you can't make your own.
<shapr>
I expect Go to be wildly successful, it's the PHP of programming languages.
<shapr>
Go is easy to learn because there's not much there. So I expect it to gain a bunch of users, and then when it gets more complicated it'll be the incumbent already.
<shapr>
awygle: I agree that Go is another take on Java, and not as good as jdk 1.0.2 :-/
<shapr>
awygle: how do you feel about Go *today* ?
<rqou>
my opinion is basically "not really relevant to anything I'm likely to be doing soon"
<rqou>
for everything that go is normally used for i would use either sneklang or rust
<rqou>
this is especially great because these are exactly the languages azonenberg hates
<shapr>
sneklang == python?
<rqou>
yeah
<shapr>
I don't mind Rust,
<shapr>
even without higher kinded types
<rqou>
yeah I'm not really a FP type
<rqou>
although i do use a lot more FP-ish ideas than some programmers because i went to $FANCY_SCHOOL
<qu1j0t3>
but you're trying to stop, right
<mithro>
I describe Go as a "language I have most wanted to like but was unable to"
<rqou>
$FANCY_SCHOOL has a little bit of a FP bias but is still pragmatic enough to not be doing type system wankery all the time
<shapr>
mithro: what did you dislike? what did you like?
<rqou>
I'm pretty sure the coding style i hate the most is "classic" OO with inheritance and overrides (e.g. azonenberg's)
<shapr>
rqou: ever tried smalltalk?
<rqou>
no
<rqou>
i looked at obj-c a tiny bit and the syntax drove me nuts
<shapr>
Python's default method return is None, smalltalk's is self/this
<shapr>
oo code in smalltalk looks more FP because you can easily chain calls together
<rqou>
i guess that's neat
<shapr>
yeah, I dug into OO for a few years, C++ isn't that close
<rqou>
of the C++/Java-style OO i think i hate inheritance the most
<rqou>
i feel it makes code really annoying to follow and is basically never what i wanted
<shapr>
which part? code re-use or polymorphism?
<shapr>
oh, hard to follow
<rqou>
no, _polymorphism_ is fine
<shapr>
yeah, it's hard to track down where exactly something happens
<qu1j0t3>
rqou: ironically, pure FP'ers will agree with you re inheritance :D
<rqou>
but azonenberg really likes this because you get "hook points" everywhere "for free"
<rqou>
except it's not really free because now you've skipped thinking about where it would be reasonable to actually have hook points
<rqou>
and this is how azonenberg's code ends up super FFI-hostile with the code flow jumping around everywhere
<awygle>
I am torn about inheritance
<awygle>
It can make it easy to make the code look like how people talk about the problem, which is huge
<rqou>
except it's not even good at that
<awygle>
But it sure does seem misused. I especially hate languages like C# forbidding free functions.
<awygle>
Too many people use classes where they want modules.
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<rqou>
e.g. I've seen a Minecraft mod (yes yes, certainly not the pinnacle of high-quality code) make a class called RotatedBB that inherited from AxisAlignedBB
<rqou>
because this allows them access to the "hook points" in AxisAlignedBB where collision is checked
<azonenberg>
Soooo
<azonenberg>
spartan7 is basically spartan6 LX's successor
<awygle>
"people write terrible code" is a valid knock on a language but not the most persuasive one
<azonenberg>
artix7 is spartan6 LXT's successor
<rqou>
but a RotatedBB clearly isn't a special kind of AxisAlignedBB
<azonenberg>
then kintex is low-end virtex, virtex is still virtex
<azonenberg>
rqou: That's an object model error
<azonenberg>
it should be BoundingBox as the base class
<azonenberg>
In which case it makes sense
<rqou>
but the problem is that i see this kind of pattern _all the time_
<azonenberg>
The solution is sane archiecture, not getting rid of OO :)
<azonenberg>
You can write bad code in any language
<awygle>
I do not understand why sane oo is so hard for so many people to grasp
<azonenberg>
awygle: me too, lol
<awygle>
At the same time I don't agree that language has nothing to do with it
<awygle>
It's hard to write insane rust :-P
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<rqou>
in my discussions with my housemate, most of these stupid inheritance trees show up after projects mature and don't get enough refactoring
<awygle>
If you have a bad object model error in Rust you just... Can't write the code.
<rqou>
because people start inheriting to get access to hook points
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<awygle>
Yeah but that's not an excuse. I spent last week fixing huge swathes of our architecture. Refactoring is achievable.
<rqou>
but because the projects can be very large it's hard to change up how the objects work
<shapr>
it's easier with tests and a refactoring browser
<awygle>
Tests are (would be) huge, yes
<azonenberg>
sorear: matthiasm seems to think ultrascale is multidie too
<azonenberg>
Which is wrong, there's multidie 7 series and monolithic ultrascale parts
<awygle>
azonenberg: do you actually hate rust, or do you just not see the advantages (or don't see them as worth it)?
<azonenberg>
I'm told that internally 7 series was called Fuji, 8/Ultrascale is Olympus, 9/Ultrascale+ is Diablo
<azonenberg>
then Everest is the new ACP or whatever the thing is called
<shapr>
I should be writing this down
<awygle>
Olympus and Diablo are great lol
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<awygle>
For entirely different reasons
<azonenberg>
awygle: I dont hate rust
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<azonenberg>
I hate refusing to work with the language a project is written in
<azonenberg>
and rewriting things for no other reason than to use your language of choice
<azonenberg>
I don't know rust, i dont want to run a project that's half rust
<azonenberg>
If i learn it, that may change
<azonenberg>
But i dont have time to right now
<rqou>
um, it definitely wasn't "no other reason"
<azonenberg>
i'm actually seriously planning to use rust for the antikernel userland down the road
<rqou>
my final architecture looks nothing like xbpar
<rqou>
i don't even use simulated annealing
<awygle>
lulz. yes I understand why you would be irritated with rqou. just wondered about more general feelings.
<azonenberg>
I dont like sneklang, because of indentation and various other things
<azonenberg>
But i have no problems with rust (yet)
<azonenberg>
Java i dislike because of the lack of standalone function support
<awygle>
I dislike Java for many many reasons
<awygle>
Execution in the Kingdom of Nouns remains relevant
<azonenberg>
It feels like trying to build a house with a blunted saw and a padded hammer
<azonenberg>
and a bunch of lincoln logs
<azonenberg>
like, its harder to hurt yourself
<azonenberg>
But that doesnt really help if the job isnt getting done :p
<rqou>
lol
<azonenberg>
In general it seems to force one particular oo model on you
<azonenberg>
one coding style
<azonenberg>
Whereas C++ gives you a toolbox and if you drill a hole in your foot, it's because you put your foot there instead of a 2x4
<rqou>
but anyways, i definitely believe that xc2par would have taken substantially longer to write in C++
<rqou>
because it really does use a lot of features that C++ doesn't have equivalents to
<rqou>
e.g. just serde has already saved me _a ton_ of work
<rqou>
e.g. azonenberg just try implementing the ability to save and load a PARGraph
<balrog>
azonenberg: it seems the biggest complaints with python are performance, really
<balrog>
(I don't consider indentation a valid complaint)
<balrog>
FFI with C++ is a problem as well, but I don't know anyone really trying to solve that problem in a mainstream language
<balrog>
(sorry Bike, Common Lisp is not mainstream enough)
<Bike>
i tune out of programming language choice talk anyway
<rqou>
yeah python is slow as shit
<rqou>
*cpython
<rqou>
but it's convenient, so whatever
<balrog>
cpython is slow; the compiled forks like pypy run behind
<balrog>
rqou: is anyone working on C++ interop in Rust?
<azonenberg>
personally i just dont see ffi as a major issue
<rqou>
anyways, half-serious opinion: using Rust is worth it just for serde
<azonenberg>
if i write something as a C++ library i expect thou shalt use C++ to use it
<rqou>
whereas i would prefer all libraries to have c-compatible interfaces with as few external dependencies as possible
<shapr>
I kinda expect some interop
<awygle>
meanwhile i see FFI as the most important issue
<rqou>
e.g. not even requiring the system memory allocator (xc2par is not at this stage yet)
<awygle>
because the lack of it _is why we keep having these (goddamn) (fucking) conversations_
<rqou>
(yes, no_std xc2par is a stretch goal)
<rqou>
given that, at the highest level of abstraction, xc2par "just" takes in an array of bytes and gives you back an array of bytes, there's no good reason why it can't be no_std
<rqou>
and given this viewpoint there's also no reason why it can't be ffi-friendly
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<rqou>
although it kinda sucks that Rust doesn't have a hook point in the compiler that runs after names are resolved
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<rqou>
which makes it incredibly difficult to write things like AutoFFI macros
<awygle>
build script? not sure when those run
<azonenberg>
rqou: but what if you want the ability to manipulate the bitstream and lut structure internally?
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<azonenberg>
i.e. for a floorplanner app or something
<sorear>
Output is bitstream, what’s the input?
<azonenberg>
you have to still have a full api
<rqou>
those run before parsing even happens
<awygle>
yeah thought so
<rqou>
azonenberg: yeah, that's called "run only some of the passes"
<azonenberg>
i mean there still has to be an api, it cant *just* be a black box single function
<rqou>
all the internal data structures are "dumb" and POD-like
<awygle>
it would be good to specify a stable set of datastructures tho
<awygle>
at some point
<rqou>
unfortunately they're not PODs because of use of tagged enums
<rqou>
stable data structures are probably not happening anytime soon
<azonenberg>
meanwhile if you used an encapsulated API, you could keep the function names/prototypes stable
<azonenberg>
and have the data structures change under the hood silently
<azonenberg>
*hint hint* :p
<awygle>
it's just a question of what you want to stabilize
<rqou>
i mean, you can just add a "stability guarantee" wrapper layer if you want that
<awygle>
do you want to stabilize the functions or the data structures?
<awygle>
data structures have the advantage that "foreign data interface" is generally pretty easy
<rqou>
yeah
<rqou>
other than the "not actually written yet" part, you can just dump the data structures into json or whatever and send that across the ffi interface
<rqou>
or one of the binary serialization formats
<rqou>
by the magic of serde, you can plug in any serialization backend you want
<sorear>
You’re looking for mrustc, although it makes no attempt to output readable code
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<awygle>
By The Power Of Serde!
<awygle>
azonenberg: what's that tiny IC right in the middle of prime routing real estate?
<awygle>
some kind of management IC?
<awygle>
temperature sensors et al?
<azonenberg>
if you mean almost dead center
<azonenberg>
thats the clock buffer
<azonenberg>
Rather than having eight oscillators scattered around the board
<azonenberg>
Which is always an option i guess, this was lower bom cost
<azonenberg>
there is a temp sensor but its on the back side and under a bunch of top side buses
<azonenberg>
So not in the way of much
<awygle>
ah
<awygle>
yeah i meant the clock buffer. if it wasn't there you could make that turn, easy. but it is actually an important thing so nvm :p
<azonenberg>
lol
<azonenberg>
yeah i might try to move it a few mm to the right though
<azonenberg>
or up
<azonenberg>
either would work
<azonenberg>
... aaand the IT guy just got me credentials to the box i'm supposed to be testing today
<azonenberg>
So i have to start actually working :p
<awygle>
bummer dude :p
<azonenberg>
But yeah as you can see its taking shape nicely
<awygle>
today is one of those days where i feel like i'm working hard, but when i look back i'm not really accomplishing much...
<azonenberg>
sounds like me on the house
<azonenberg>
:p
<shapr>
I'm tempted to start live tweeting my Go learning
<shapr>
inconsistent syntax: I have to use *p to modify an int stored at p, but I cannot use *p.X to modify a field in a struct stored at p
<rqou>
lol azonenberg and your friggin house
<shapr>
azonenberg: is there a full list of your CAPSPROJECTNAMEs ?
<azonenberg>
shapr: nope
<shapr>
aw, I was gonna write a lambdabot plugin to generate more
<azonenberg>
Off the top of my head... LATENTPACKET is the switch stuff, MARBLEWALRUS is the (mostly shelved until i finish higher priority stuff) FPGA cluster, STARSHIPRAIDER you know
<azonenberg>
REDTIN is the ILA core
<azonenberg>
I dont have a name for the scope client app
<azonenberg>
the DSO project doesnt have a name yet
<awygle>
TRAGICLASER
<azonenberg>
yes, that
<awygle>
i still recommend TRAGICBACKSTORY for the scope client
<rqou>
nobody likes my style of stupid names?
<azonenberg>
That would imply they were related under the TRAGIC* umbrella
<awygle>
well, that's the project that forced you to write it
<rqou>
e.g. "Bus Armada"
<azonenberg>
If anything, that name would be for if i ever got masochistic enough to bitbang a 1000baseT PHY
<azonenberg>
awygle: um, no
<azonenberg>
scopeclient has existed since the early days of antikernel
<azonenberg>
originally it was for REDTIN and my rigol
<rqou>
or ShinyKinglerPAR (which azonenberg has vetoed me from writing)
<shapr>
rqou: what are your names?
<rqou>
usually some stupid joke
<azonenberg>
The only thing i did recently to it was add 100baseTX and eye diagram support
<azonenberg>
rqou: totally unrelated
<azonenberg>
What's Professor Oak's favorite database?
<shapr>
is REDTIN in the antikernel-cores repo?
<rqou>
"Bus Armada" = "an attempt to defeat the bus pirate that will just end up being a huge failure after a huge expenditure of resources"
<awygle>
rqou: shiny kingler makes it less like ferris tho
<awygle>
shiny kinglers are green
<awygle>
(apparently)
<shapr>
rqou: I love that name
<shapr>
and the narrative that goes with it
<rqou>
yeah, green, like greenpak :P
* awygle
harrumphs
<rqou>
it's also an evolution
<rqou>
:P
<rqou>
hence why it's not ShinyKrabbyPAR
<azonenberg>
rqou: PokeMonGo DB
<azonenberg>
:D
<rqou>
but anyways azonenberg has vetoed ShinyKinglerPAR
<shapr>
bwahaha
<shapr>
azonenberg: did you just make that up?
<azonenberg>
Yes
<azonenberg>
Lol
<awygle>
youch that's bad azonenberg
<azonenberg>
shapr: the redtin capture module is in antikernel-ipcores, the client code is currently living in the main antikernel repo pending the eventual split of scopeclient and scopehal into a separate repo
<shapr>
put it on twitter and I'll retweet
<shapr>
otherwise I'll put it on twitter and credit you :-P
<shapr>
ok, that explains why I couldn't easily find REDTIN
<azonenberg>
shapr: yeah originally i was full google monorepo
<azonenberg>
i'm in the process of migrating some standalone projects out of the antikernel repo so they can be used on non-antikernel projects
<shapr>
that's good for interdependent projects
<azonenberg>
Generally there's one way dependencies
<azonenberg>
antikernel uses everything
<azonenberg>
but as i've refactored there's not much dependency the other way around
<shapr>
some noob who was here before me checked in several gig of documents
<shapr>
and management won't let us restart the git repo
<shapr>
good thing there's --depth=1 but when grabbing history, there's a big wait :-(
<shapr>
oh, another bad thing about Go is package management
<shapr>
It grabs HEAD github.com by default
<azonenberg>
shapr: tweeted, lol
<shapr>
so different builds on different machines at different times won't be the same unless you vendor your dependencies
<azonenberg>
shapr: eeeew
<shapr>
Go just decided on how to do versioning ... last week?
<shapr>
I turned down a job at a startup a few months back because they thought vendoring their deps wasn't important
<shapr>
All their deployments are on cargo ships wandering the world, all written in Go
<shapr>
no way I want to debug that bear trap
<awygle>
i just pick words for project names
<awygle>
currently i have anansi, aria, and fondue
<awygle>
just as some examples
<shapr>
all my boxes are named for chaos gods, so I have anansi right now
<shapr>
and veles and leviathan
<azonenberg>
My host naming schemes are dependent on who owns the box and what it's used for
<awygle>
loki is passé now lol
<azonenberg>
Personal client systems: Symmetric ciphers
<awygle>
my boxes are all named from Raildex currently actually
<shapr>
coyote and eris are my favorite chaos gods, but kali is third
<azonenberg>
for a brief stint we were using physicists, maxwell was the only one of those i think
<shapr>
google assistant :-P
<azonenberg>
Then school-owned machines i adminned were, in a dig at the administration, famous scandals and embezzlers
<azonenberg>
madoff, ponzi, enron, watergate
<Bike>
kind of tickling the dragon's tail with the AI one
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<azonenberg>
(security.cs.rpi.edu is still hostnamed watergate last time i checked)
<awygle>
my dev container and dev vm are accelerator and dark-matter, my router is touma, my git server is index. i probably wouldn't set this up this way today, but i was a) even more of a weeb and b) really into raildex when i put this network together
<azonenberg>
Storage systems are famous libraries
<shapr>
I wonder if there's a collection of names of Godel attacks? Seems to me roko's basilisk is a Godel attack
<azonenberg>
right now i have Congress after the LoC
<azonenberg>
Alexandria is next on my list
<Bike>
"godel attack"? is that a term?
<shapr>
I think so
<shapr>
have you seen the comp.basilisk FAQ?
<azonenberg>
then company-issued machines for my use are NSA programs or classified cryptosystems
<shapr>
the GPL fits into what I define as goedel attacks
<Bike>
i don't see what roko has to do with godel, really
<azonenberg>
oh, then VPSes or other DMZ machines are gods of the underworld
<shapr>
Bike: have you read GEB?
<azonenberg>
thanatos, charon, pluto, hades
<Bike>
it's called a basilisk because it only affects you if you look at it, but it's not about self reference, or true but unprovable statements, or anything
<azonenberg>
And $wife's machines are artists, currently davinci is the only one
<Bike>
i have. i'm pretty sure roko was not involved
<Bike>
though it has been a while
<shapr>
do you remember how the crab kept blowing up the record players with records that were unplayable?
<Bike>
vaguely
<Bike>
i mean, by now i just know the math
<shapr>
For me, any attack that uses the system against itself is a godel attack, like roko's basilisk, the BLIT, and the GPL
<Bike>
how is roko's basilisk using "the system" against itself?
<Bike>
"the system" being the human mind in this context, i guess
<shapr>
and the artificial suppositions of less wrong as well
<shapr>
they banned any mention of roko's basilisk, that amuses me to no end
<Bike>
it's pretty fuckin hilarious, yeah.
<awygle>
wow
<awygle>
i've never googled this before
<Bike>
what, roko?
<awygle>
just seen the name thrown around
<awygle>
yeah
<Bike>
yeah, it's pretty great.
<rqou>
hmm azonenberg: xc2 sram programming is giving me inconsistent behavior, do you know anything about that?
<Bike>
inventing a silly religion from first principles
<awygle>
this is like one of those horror stories you tell as children, that when you think about them cease to make any sense, but which are coded in such a way that they still read like horror stories
<azonenberg>
rqou: i played with it briefly
<azonenberg>
but not enoguh to be able to comment in any detail
<rqou>
I'm just in general seeing weird "not working" behavior
<rqou>
but sometimes it's fine
<awygle>
shapr: what is this comp.basilisk thing? a usenet version of SCP?
<azonenberg>
i know i had such issues when i tried to do partial reconfiguration
<azonenberg>
But i never tried full sram programming
<Bike>
SCP's memes are pretty obviously derived from BLIT and similar
* awygle
feels young, briefly
<shapr>
awygle: sort of.. it's a short sci-fi story
<shapr>
from long years ago
<shapr>
99 I think?
<Bike>
i thought it was 80s
<Bike>
anyway the titular basilisk is an scp kill meme
<awygle>
looks like december 99 per the faq
<Bike>
or maybe stop meme? i don't remember
<Bike>
it either kills you or makes you catatonic
<awygle>
stop the meme, i wanna get off
<shapr>
the BLIT bricks your firmware
<shapr>
has anyone here not yet read Snow Crash?
<Bike>
the other day i read "A Colder War" and it was like wow, SCP is super derived from this
<Bike>
funny how that goes
<awygle>
i wish snow crash had been sold to me differently
<Bike>
how was it sold to you?
<awygle>
people kept mentioning it in the same breath as Neuromancer
<shapr>
uhh
<awygle>
they are wildly disparate
<sorear>
twofish was the aes finalist, threefish was a block cipher at the core of the skein sha3 finalist
<shapr>
yes
<Bike>
the snow crash sequel literally starts with a parody of cyberpunk, lol
<sorear>
i have not read either
<awygle>
so i never made it past the first chapter of snow crash the first ~4 times i read it
<shapr>
Gibson and Stephenson have different approaches
<awygle>
or tried to read it rather
<shapr>
awygle: try starting with interface or zodiac?
<awygle>
shapr: i've finished it now
<shapr>
oh
<shapr>
I read too much
<awygle>
and it's great, it's just... very not neuromancer :p
<sorear>
threefish is a pretty neat cipher in its own right, if you need a 256/512/1024 bit block size i'd recommend it
<shapr>
have you also read ... oh what's it called A Young Lady's Primer?
<shapr>
oh, diamond age
<awygle>
no, i own diamond age but haven't read it yet
<shapr>
I rarely have unread books
<shapr>
that's my drug of choice
<awygle>
stephenson is pretty hit or miss for me. i loved snow crash and cryptonomicon but bounced hard off of Anathem and hated Seveneves
<Bike>
the way i had another reader describe it to me was you like snow crash and stuff and then as you continue, you slowly realize, horribly, that he was serious
<shapr>
(I refuse to read things if I don't have permission)
<Bike>
is goodkind the one with the chicken of evil
<awygle>
Bike: yes lol
<shapr>
I've spent way too much money on baen.com
<awygle>
shapr: i read all the honor harrington books on baencd, and for some reason i completely love them
<Bike>
geez, i hope people don't read stross as that bad
<awygle>
there are tons of things wrong with them but *shrug*
<shapr>
oh hey, that series just concluded
<shapr>
finally
<shapr>
I talked to Toni about why it went on so long, she said Honor was supposed to die in book three or four, but he couldn't let go
<shapr>
Toni is Baen's editor
<shapr>
she's really cool
<Bike>
what exactly is on this site
<awygle>
she was supposed to die at the Battle of Manticore, for sure, he says so in the afterward for that book
<Bike>
books published by Baen?
<awygle>
i don't think it's over though? there's a new one coming out in october
<shapr>
Bike: CDs that were in hardcover books released by Baen
<shapr>
and Baen has explicitly given permission for redistribution
<Bike>
and... the CDs have the texts, or...?
<shapr>
yes, in html
<awygle>
and also epuh
<awygle>
*epub
<Bike>
nice
<shapr>
it's a large amount of reading, took me a whole summer
<awygle>
some of them are ARCs, which occasionally leads to some inconsistencies, but hey, free
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<shapr>
I've enjoyed almost all the books published by baen
<shapr>
with a few exceptions
<shapr>
I should really drop by stories into the slush forum on baen's bar
<shapr>
my*
<awygle>
doesn't baen publish a bunch of john ringo that's like... really bad?
<shapr>
I enjoy it.
<shapr>
but it does have a very bad rep, yes
<shapr>
You mean the Kildar series, specifically
<shapr>
Though Monster Hunter International is the same kind of wish fulfillment
<awygle>
i enjoyed live free or die. i read the one with the evil centaurs, which was... ok. i didn't check out the "super edgy" one whose name i can't remember but is probably kildar
<shapr>
evil centaurs?
<awygle>
posleen? something like that?
<shapr>
oh right!
<shapr>
the aldenata series
<shapr>
yeah, that was fun
<awygle>
"i want world war one with aliens, let me design my tech to allow that to happen"
<shapr>
I enjoyd the 1636 world for about five books, then I over it.
<shapr>
I wish tor.com or others would release their books in html format
<awygle>
my father kept ttrying to get me to read the weber/ringo collab "march upcountry" but i just can't get into it
<shapr>
I refuse to read encrypted, etc
<shapr>
oh I loved that series!
<shapr>
march upcountry is book two or three
<shapr>
also very wish fulfillment
<awygle>
is it? i thought it was upcountry, sea, stars
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<shapr>
wikipedia says you are correct and I was wrong
<shapr>
whoops
<awygle>
lol
<awygle>
##openbookclub
<shapr>
ha
* awygle
closes irc, gets back to work
<shapr>
I should go home and stop being off topic
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<rqou>
O_o
<rqou>
ping azonenberg
<azonenberg>
?
<azonenberg>
rqou:
<rqou>
i found a design where ise will set the input and output voltages differently on xc2c32a
<azonenberg>
o_o
<azonenberg>
how
<azonenberg>
i tried mixing iostandards and just got fitter errors
<rqou>
afaik i got it by setting the default io standard to 3.3V and then having one bank be entirely empty
<azonenberg_work>
interesting
<azonenberg_work>
maybe it doesnt set the istandard bit if theres no ibufs there or something?
<rqou>
that's what it looks like yes
<rqou>
but it'll still set the output voltage
<azonenberg>
so what if you have a bank thats entirely outputs
<azonenberg>
then inputs in the other bank
<rqou>
I don't know
<rqou>
you can try it yourself :P
<azonenberg>
So far though, it looks like always setting vin=vout is legal
<azonenberg>
they're just maybe dontcare if you dont have ibufs or obufs
<rqou>
but my guess is that too high a vccio can maybe damage the output drivers
<kc8apf>
why did Xilinx pick this crazy addressing scheme for config memory?!?!?!
<rqou>
but the input drivers need special anti-latchup and stuff anyways for the hotplug capability that people expect in cplds
<mithro>
Wire + LUT bitstream output from VPR is shown to be equivalent to input using Yosys!
<mithro>
Now for clocks!
<sorear>
nice!!
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<azonenberg>
kc8apf: which scheme? for cplds or fpgas?
<rqou>
so maybe for inputs it doesn't matter if you apply too high a voltage
<kc8apf>
xc7
<azonenberg>
kc8apf: it makes sense for partial reconfig, doesnt it?
<kc8apf>
it's a geographical routing
<azonenberg>
well duh
<azonenberg>
keep in mind the addressing is designed by hardware people
<kc8apf>
that you need to know how to iterate over
<rqou>
anyways, do you think you can be slowly frying the obufs if you set the default voltage to 1.8V and then apply a high vccio?
<kc8apf>
and then sometimes, just skip 2 frames, because undocumented reasons
<rqou>
even if you never enable a driver?
<azonenberg>
rqou: conjecture: yes
<azonenberg>
i think ibufs and obufs can both fry if in the low voltage mode and fed with 3.3
<rqou>
i don't think ibufs can
<azonenberg>
what i think is happening is you're activating a pass fet between vcco and two internal rails
<azonenberg>
vcco_hi and vcco_lo
<rqou>
since they need esd and anti-latchup and crap
<azonenberg>
And enabling io drivers with different oxide thickness
<azonenberg>
i.e. the fast low voltage drivers may not survive 3.3 for extended time periods
<rqou>
anyways, why have i not seen any kind of warning about anything like this?
<azonenberg>
Dont know
<azonenberg>
maybe it only fries unused ibufs
<azonenberg>
and if you dont later start using them its harmless?
<azonenberg>
or maybe it doesnt actually kill them?
<azonenberg>
Meanwhile, on the flip side... i would expect that if you had an ibuf configured to 1.8V
<azonenberg>
and feed it 3.3V on vin (not vcco)
<mithro>
Anyone want to write me a simple little python script to translate form pcf files into the .place format vpr uses? :-P
<azonenberg>
it may not survive that
<azonenberg>
again i think its double oxide thickness
<rqou>
can we please get netlist recovery on the io cells?
<azonenberg>
rqou: i gave it to some of my students as a homework assignment
<azonenberg>
nobody finished, the photos didnt have enough detail in some spots
<rqou>
yeah i remember that
<azonenberg>
But i can send you the imagery i have if you want it
<rqou>
ugh i really need to fix the .crbit tools to properly prep files for uploading
<rqou>
(it's missing sec/done bits)
<rqou>
also, mis-setting the sec bits also causes funny behavior