<q3k> >jupiter
<kc8apf> hah
<q3k> not the equipment you're thinking of :P
<kc8apf> Juniper
<q3k> tell the owner he's an idiot
<q3k> he's/she's
<q3k> no, but seriously, nobody needs cisco or juniper for less than 10GbE of traffic in 2018
<q3k> >Because FCIX was founded to save some amateurs some money, so paying for an ASN kind of goes against that objective. Do you have a spare ASN you’re not using?
<q3k> oh wow
<q3k> it's literally 100eur per year to get one
<q3k> from a LIR
<q3k> that's even cheaper than i am :P
<q3k> kc8apf: i can probably help them out at least with an ASN if you get us in touch
<q3k> kc8apf: i run https://bgp.wtf/, we're a LIR, we're Okay People
<q3k> that's RIPE, not ARIN, but eh, we can figure things out
<kc8apf> hit up contact@fcix.net
<q3k> should I CC you?
<kc8apf> nah. I don't peer with them. I just know one of the founders.
<q3k> j
<q3k> *k
<kc8apf> they're cool folks. Kenneth tends to blog about odd corners of IT: http://blog.thelifeofkenneth.com/
<q3k> sent them a mail
<kc8apf> :)
<q3k> interesting that they're going for root-servers and not one of the large cdn providers
<q3k> we peer with AS15169 and it makes watching cat videos so fast
<q3k> (also traffic to google cloud is basically wire speed)
<kc8apf> I just want 1Gbps to my house
<zkms> wait what, an AS number is 100EUR/year? I didn't know that >_<
<kc8apf> an IP block would be nice too
<q3k> zkms: yes, ask a local LIR (like us :) )
<q3k> kc8apf: you can get shared medium 1gpbs super cheap these days
<q3k> kc8apf: but enjoy your 32:1 oversubscription
<kc8apf> I shopped around. Not a whole lot of providers have any sort of last mile into residential
<kc8apf> Comcast quoted $2000/month
<q3k> lol usa
<kc8apf> I keep meaning to spend some time on Google Earth seeing if I can work out line of sight to FMT2
<q3k> i'm afraid placing an anternna there will be just as expensive
<q3k> are there no small (W)ISPs around you?
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<kc8apf> antenna charge isn't huge.
<rqou> there are some in some areas
<rqou> afaik they all suck
<kc8apf> there are a few WISPs but they have terrible pricing
<rqou> Berkeley is getting gigabit fiber just as I'm moving out, but i haven't seen any of their physical plant anywhere so idk if it's real
<q3k> you might still want to talk to them about stuff
<q3k> they might offer you a better deal for if you ask something low maintenance from them
<q3k> (ie just want metro ethernet and a public /28, don't need tech support for your CPE, etc)
<q3k> or it turns out they'll be just okay with setting up BGP for you for free
<q3k> *BGP with you
<kc8apf> I can get most of that through Comcast Business. I had a /29 at my previous house.
<q3k> right, but then you end up giving comcast money
<q3k> i'd personally rather support a local isp and pay a bit extra for that
<kc8apf> If sonic was in my area, I would
<q3k> heh, i just image searched as204880, and it's mostly my twitter shitposting
<q3k> i'm okay with this
<rqou> yeah, sonic is the one claiming to now have gigabit fiber in Berkeley
<rqou> maybe they're only just-in-time installing their last mile
<q3k> 'gigabit fiber' can mean anything from metro ethernet to GPON to FTTC and VDSL :(
<q3k> these days it mostly means GPON and that's cheating
<rqou> there's no way VDSL can get gigabit over those lines
<kc8apf> Sonic leases AT&T lines. They're doing FTTN for most offerings
<q3k> rqou: no, but there's Gigabit Fiber to the DSLAM and there's 100mbit between you and the DSLAM :)
<rqou> there's no way to do that either
<q3k> (seriously, a national telco in Poland was using this argument)
<q3k> what, 100mbit?
<q3k> absolutely doable
<q3k> if the DSLAM is in your building
<rqou> AT&T's limit for our apartment was 6mbps
<q3k> which is what VDSL is for
<q3k> right, but that's probably shitty ADSL on shitty copper to a DSLAM that's at a local exchange
<rqou> this is the only wire entering the unit
<q3k> what the hell is this terminal system anyway
<rqou> lol
<kc8apf> huh, they claim their fiber offering is FTTH over their own fiber
<q3k> kc8apf: still probably GPON
<kc8apf> yup
<rqou> this crappy photo is Comcast's wiring: https://photos.app.goo.gl/tkbZhs3owqi1Qbcj9
<q3k> rqou: average 0 fucks given cable coax
<q3k> seen worse
<q3k> docsis still should bo _okay_ on this
<q3k> (i'm getting 300mbps on similar grade coax)
<rqou> docsis is doing quite poorly too
<sorear> How upgradable are ftth systems? Could they install 10G line cards later without redoing the last mile wiring (assuming economic conditions are met)
<rqou> I'm pretty sure some noise is leaking in from a neighbor or something
<q3k> sorear: yes
<q3k> sorear: you need to upgrade the OLT and ONU/ONTs from GPON to 10GPON
<rqou> btw this is the main breaker for the unit: https://photos.app.goo.gl/iYBdXWGDnTHK1NMs8
<rqou> the one on the right is our unit
<rqou> note the number on it
<q3k> sorear: iirc should work over the same fibre/splitters
<rqou> this explains the passive-aggressive breaker tripping that was happening months ago :P
<q3k> >The 10 Gigabit PON wavelengths (1577 nm down / 1270 nm up) differ from GPON and EPON (1490 nm down /1310 nm up), allowing it to coexist on the same fibre with either of the Gigabit PONs.[5]
<rqou> although i seem to get the impression that my apartment was somewhat uniquely worse than average :P :P :P
<q3k> rqou: usually poor docsis performance is due to mismatched attenuation on the coax
<rqou> meaning?
<q3k> it's fucking radio magic i can't explain this
<rqou> i did mess around with some splitters a bit and things got a little bit better
<q3k> but all three apartments i've been to I just had to get rid of excess splitters/attenuators and got speed bumps
<rqou> well, i really wanted to unplug the neighbors but I don't think they'd appreciate that :P
<q3k> main problem with this ISP really is that they don't have open peering
<q3k> so way too often my packets end up taking the scenic route
<rqou> i did remove our daisy-chained splitter and signal levels got high enough that docsis would still work most of the time
<rqou> occasionally one channel will still flap and the modem starts to perform like shit in that case
<awygle> Buildings often neither terminate nor isolate after their shitty home depot splitters, leading to bad impedances
<awygle> Did I tell this channel about "I make boost"?
<rqou> hmm interesting paper i just came across
<rqou> apparently you can break some TRNGs based on ring oscillators by injecting sine waves into the power supply
<rqou> at some frequencies you can get the ring oscillators to lock onto the injected signal
<rqou> i remember whitequark observed this on greenpak, but i didn't think this could actually be _exploitable_
<azonenberg_work> rqou: i tried to build a ring osc trng on spartan6
<azonenberg_work> and observed phase locking to each other based on (presumably) PDN resonances
<azonenberg_work> abandoned the project because i saw no way to make it secure
<rqou> well, apparently even smartcards haven't succeeded yet
<azonenberg_work> kc8apf: re comcast
<rqou> or at least they haven't back in 2009
<sorear> If you can control the power supply that well, you’re not really hurting for options
<azonenberg_work> i'm getting i think 75/15 Mbps at the new place with a single IPv4 address and... a /56 of IPv6?
<azonenberg_work> But upload b/w is hard to come by
<azonenberg_work> even at gig down i think you get like 50M up
<sorear> Suggestion: decoupling caps and/or chokes
<azonenberg_work> (yay docsis)
<azonenberg_work> i want fiber / met eth but i dont think either are available here
<azonenberg_work> I continue to dream... one day, someone will run an uncapped 1000baseLX pipe to my house and bill me at 95th percentile bandwidth
<rqou> somebody on birbsite (i think it was @alt_kia?) posted a slide deck that was from some team at Standford trying to research how to squeeze >1Gbps by using crappy POTS wiring as a waveguide and sending signals _between_ the wires
<rqou> because last mile in the US is just so ridiculously expensive
<sorear> Yes
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<rqou> yes to which part?
<sorear> https://mobile.twitter.com/alt_kia/status/929819452987785216 still the top hit for Goubau line
<sorear> All of the above
<kc8apf> I've thought about getting the single v4 and a /56 of v6 from Comcast. It was extremely convenient to access service at home.
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<azonenberg_work> Yeah i am planning to set up a KVM or something box in my DMZ
<azonenberg_work> and host a bunch of stuff internally
<awygle> I could get gigabit (allegedly symmetric) but it would be 20$ more and the 40mb I have now is more than I need
<azonenberg_work> gig symmetric???
* azonenberg_work wants that
<azonenberg_work> but out here in kitsap-land pretty sure thats a pipe dream
<sorear> I didn’t even have to from:alt_kia it
<awygle> I think so? I'll confirm when I get yet another ad
<awygle> I wish I could just pay for the internet portion but I think they want me to get cable also or pay just as much as If u had
<awygle> azonenberg_work: yeah it definitely is, just like buying a house in Redmond :-P
<rqou> i need to lern2optics better
<rqou> goddammit azonenberg you said nothing when i was joking about making a Red/Blue/White Magic Probe and here you are now asking about PIC debug protocol
<rqou> afaik it's proprietary and undocumented
<rqou> hmm, there must be some other kind of different bug somewhere
<rqou> at least running this is idempotent lol
<rqou> oh lolol i found a major bug
<rqou> it turns out that a mux can't route a wire to itself :P
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<azonenberg_work> rqou: i'm doing a survey paper at $work
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<azonenberg_work> on embedded systems program/debug protocols, code protection, and bypass techniques
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<azonenberg_work> At this point in the game i'm not trying to find any new attacks
<azonenberg_work> Just get the lay of the land
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<rqou> aka "making 'protected' public?" :P
<rqou> or are those not in scope?
<azonenberg_work> not just that
<azonenberg_work> (and this isnt for public release, its internal for hte moment)
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<azonenberg_work> basically i want to know, for *every* common MCU family we see
<azonenberg_work> What protections does it have?
<azonenberg_work> What exactly is locked out by the protections?
<rqou> stm32: obviously not enough
<azonenberg_work> What protocols are provided for accessing ram, flash, etc in an unlocked chip, that might be useful as points of attack?
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<azonenberg_work> And how can you tell what protection level is applied in an unknown device?
<rqou> is ioa going to work on systematically attacking code protection at some point?
<azonenberg_work> Dont know, if i did i probably couldnt say
<azonenberg_work> This is fallout from a previous project in which we had a chip that we couldnt read, but we also couldnt say for sure it was locked
<rqou> lol
<azonenberg_work> And we want to eliminate that uncertainty
<azonenberg_work> But personally i would also like to add low-level probe support for various things to jtaghal
<azonenberg_work> So you can do things like, if flash is read protected
<azonenberg_work> try to read ram
<azonenberg_work> or cpu registers
<rqou> *cough* *cough* stm32
<azonenberg_work> That is certainly a potential target but again, at this point i'm not going after any one family
<azonenberg_work> i want to know a little bit about everything
<rqou> i'm just particularly unhappy about it because properly securing it is ridiculously bad
<azonenberg_work> Lol
<rqou> unless you set permanent jtag disable
<rqou> i assume that might work
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<rqou> azonenberg_work: did the inspector ever come by?
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<azonenberg_work> No
<azonenberg_work> i guess tomorrow
<azonenberg_work> i called the office earlier today and we were still in the pending pile for the inspector
<azonenberg_work> i.e. not picked up for the day's run
<rqou> wtf
<rqou> but they promised you yesterday?
<azonenberg_work> They promised nothing
<azonenberg_work> they said when i scheduled it that it would go in the inbox monday
<azonenberg_work> And that typical service times were same- or next-day
<rqou> ah ok
<azonenberg_work> Today is apparently not typical
<azonenberg_work> the *city* inspector, otoh, committed to monday AM
<azonenberg_work> for the caulk/seal inspection
<azonenberg_work> We're installing window trim now and should be done well before monday
<azonenberg_work> Might even be able to do framing inspection the same visit but that's probably optimistic
<azonenberg_work> Also, packing up
<azonenberg_work> back on main nick in a bit
<rqou> wait, that's a separate thing?!
<rqou> framing inspection?
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<azonenberg> Yeah
<azonenberg> Gotta make sure the place isnt gonna collapse
<rqou> ok, so for project chibi
<rqou> most of the interconnect->interconnect wires are fuzzed
<rqou> basically none of the interconnect->logic or logic->interconnect is fuzzed
<rqou> what do you think should happen next?
<rqou> analysis or more fuzzing?
<azonenberg> Crunch the data you have and try to discover patterns?
<azonenberg> Can you do io-to-io routing yet?
<rqou> so analysis
<azonenberg> i.e. go from pin 1 to pin 2
<rqou> yes, io-to-io routing is totally doable
<rqou> that's how the interconnect fuzzing was done in the first place
<rqou> er, clarification
<rqou> yes, except the input cannot be on the right hand side :P
<rqou> (the output can)
<rqou> er, the input can be on the right hand side, but only some of the pins :P
<rqou> this is because the way the right hand side enters the fabric is slightly different
<azonenberg> lol so you dont know that last bit yet?
<rqou> yeah, but i figured it wasn't that important
<rqou> so, afaict every "4x2 box" mux is exactly the same
<rqou> all 13-1 muxes
<rqou> just with different mirroring H/V
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<azonenberg> :)
<rqou> i still need to confirm this though
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<rqou> wtf
<rqou> this is really confusing
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<rqou> wut
<rqou> azonenberg: ok, i was wrong
<rqou> "down" bits can have two one-hot bits
<rqou> unless of course something else is going on
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<rqou> ok, something wrong is happening for sure
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<rqou> azonenberg: last column seems to be mirrored?
<rqou> would there be any good reason for that?
<azonenberg> Totally plausible, would have to see die layout
<azonenberg> but asics mirror things all the time in layout
<rqou> hmm, total speculation but
<rqou> what if the "acutal logic" and the "interconnect" are primitives designed separately
<rqou> and those are the actual units that get tiled
<rqou> no wait, that doesn't quite solve anything
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<rqou> azonenberg?
<rqou> (note that some IO_DATAIN and LE_BUFFER will be missing, this is known)
<rqou> ok, afaict the row wire permuting actually means something
<rqou> it seems pretty consistent that muxes connect to the same _logical_ wire number as you move around the array rather than the same _physical_ wire number
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<pb_> rqou: is right side of wirerpt19.txt supposed to be closer to hardware?
<rqou> left side
<rqou> right side is quartus naming
<pb_> rqou: have you done mapping? if not look at twitter notifs.
<rqou> what do you mean?
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<rqou> pb_: i don't see any relevant notifications?
<rqou> heh, some of that certainly looks familiar
<rqou> were you working on this before, or?
<pb_> no, just a bit of training.
<azonenberg> rqou: that makes sense
<rqou> pb_: so what exactly are you currently working on?
<azonenberg> they probably have >1 physical layout but its logically the same
<rqou> azonenberg: which part makes sense?
<azonenberg> Having muxes tied to the logical wire
<pb_> i plan to do single-script minimal ice40 "toolchain", for purely educational purposes.
<rqou> azonenberg: but weird things happen as you move across X
<rqou> it doesn't stay consistent anymore in that case
<azonenberg> huh
<pb_> no promises tho. i already twice sidetracked into deep theoretical stuff from which i likely will not get out :)
<rqou> azonenberg: nvm
<rqou> apparently it only changes for the first column?
<rqou> which is where the IOs are
<rqou> azonenberg: any guesses as to why the physical layout permutations are arranged in neat checkerboards?
<rqou> also, columns seem to behave differently?
<rqou> azonenberg: columns seem to be consistent with using the "physical" index?
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<azonenberg> rqou: checkerboards?
<rqou> oh oops forgot link
<azonenberg> sounds like probably mirroring to keep power or clock or something together
<azonenberg> yeah that smells like a physical layout optimization
<azonenberg> but i cant say what
<rqou> it's not any kind of "neat" permutation either
<rqou> unlike the ice40 "pairwise-crossing"
<azonenberg> i feel like there's some kind of pinwheel/swastika shaped routes in there
<azonenberg> could be way wrong but thats the impression i get
<rqou> what do you mean?
<azonenberg> horizontal then vertical
<rqou> er, afaict every wire is only horizontal or vertical
<azonenberg> yes but think about long parallel buses
<rqou> that's what i've been assuming in basically all of my fuzzers
<azonenberg> between tiles
<azonenberg> they have to cross
<azonenberg> on different layers
<rqou> right?
<azonenberg> but they also all have to get down to the transistor layer
<rqou> sure?
<azonenberg> So there might be some fun in which the layer changes occur at different places or something
<azonenberg> Dont know, just thinking out loud
<rqou> but it seems very systematic still
<rqou> why wouldn't it be the same on every tile?
<azonenberg> It does, its definitely a repetitive pattern
<azonenberg> I feel like it has to do with mating
<azonenberg> the left and right of each tile arent the same
<azonenberg> maybe they have horizontal and vertical rotation/mirroring or something going on within the tile even if its not reflected in the config
<azonenberg> idk
<rqou> but wouldn't things be easier if every tile were the same?
<azonenberg> Not necessarily
<azonenberg> think about what coolrunner would look like
<azonenberg> if the left and right FBs were the same :p
<azonenberg> vs mirrored
<rqou> hmm
<rqou> why are there _3_ permutations
<rqou> not 2?
<azonenberg> trying to design a single tile that has straight-across routing with (say) inputs and outputs at the same Y position each point
<azonenberg> etc
<azonenberg> woudl be hard
<azonenberg> I dont know why 3
<azonenberg> i just know, it's almost certainly related to physical layout and if you had the GDS or a decap you'd understand immediately
<azonenberg> notice that red tiles are always above blue ones for example
<azonenberg> and blues are above green
<azonenberg> But reds are left of green
<azonenberg> The tiles are designed to mate in that particular combination
<rqou> hrm, in the cyclone 1 decap everything looks the same
<rqou> maybe max v is "cost-optimized"
<azonenberg> it might just be on the newer process they had to change something?
<daveshah> Lattice and SiliconBlue both managed regular tiles on their cost optimised processes
<rqou> azonenberg: so at this point what do you think is the best way to proceed?
<rqou> fuzz the remaining bits, or try and apply more human brain?
<rqou> or write tools to perform more analysis?
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<azonenberg> rqou: dont know
<azonenberg> i'm falling asleep
<azonenberg> been up for 19 hours now
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<azonenberg_work> rqou: what's a separate thing? framing inspection?
<azonenberg_work> caulk?
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<mithro> q3k: Since you love protobuf so much, do you want to do me a protobuf schema which can represent the vpr rr_graph format described here -> https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#routing-resource-graph-file-format-xml
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<q3k> -ENOTIME I'm afraid ,_,
<q3k> VPR/VTR is one hell of a codebase and I really can't expend the effort to jump into it
<rqou> random complaint: _why_ does gimp's "Fonts (this may take a while)" step take so long?
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<pie_> isnt capnproto the new better protobuf
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<q3k> kc8apf: are proto3 maps haram or what? https://twitter.com/kc8apf/status/1009491707287617537
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<whitequark> pie_: flatbuffers
<kc8apf> Feels awkward to split the names from the rest of an object
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<q3k> kc8apf: maybe? that's how the json format does it, too
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<azonenberg_work> rqou: passed rough electrical inspection yay
<rqou> woot
<rqou> so you can finally start putting drywall up?
<azonenberg_work> He found a few minor things he wanted fixed but nothing that was enough that he needed to come back
<azonenberg_work> so we're on the honor system for those :p
<azonenberg_work> one missing nail plate, et
<azonenberg_work> And no, lol
<awygle> YA HOO (mario kart toad voice)
<azonenberg_work> We have the city inspector coming monday to inspect caulk/sealing and hvac
<azonenberg_work> So we have until then to finish the fireblocking, install new windowsills and caulk around them
<rqou> wtf so much inspecting
<azonenberg_work> and start doing the last tidbits of framing
<azonenberg_work> Then once that's done we can do the framing inspection, at which point we can begin hanging the insulation that is currently sitting on our driveway
<azonenberg_work> then THAT has to get inspected
<azonenberg_work> and we can hang drywall :p
<rqou> WTF
<rqou> way too much inspecting
<azonenberg_work> Having seen the way this place was built previously
<azonenberg_work> i'm glad there are inspections :p
<awygle> this is why you generally pay people to do this kind of thing
<awygle> actually, scratch that - this is why you generally pay people _so much_ to do this kind of thing :p
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<rqou> azonenberg_work have you considered just not pulling permits? :P
<rqou> also, just out of curiosity, did the inspector have any "interesting comments" about your design choices?
<azonenberg_work> He said it was unconventional but had no problems with it
<azonenberg_work> He didnt like the small handy boxes for the light switches, but my calculations said i was at 15.8 cubic inches of fill
<azonenberg_work> and the boxes are rated at 16.3 of capacity
<azonenberg_work> so i'm baaaarely legal :p
<azonenberg_work> Re not pulling permits, i'm enough of a realist about my skills
<azonenberg_work> that i want the inspections don e:p
<azonenberg_work> if i was an el cheapo house flipper maybe, but i'm living here myself
<azonenberg_work> i care
<rqou> so you're not a human trafficker slumlord? :P
<azonenberg_work> Well... i did take this chick from walmart and drive her 3000 miles away because she was cute
<azonenberg_work> But then i married her :p
<rqou> lolol
<azonenberg_work> And i cant afford to buy a slum
<rqou> start by owning an Indian restaurant :P
<rqou> move up to being the second-largest landowner in the city :P
<azonenberg_work> Kinda surprised he didnt try to buy berkeley
<rqou> found an engineering school in india and be treated like a god :P :P
<jn__> Zonenberg's Fried Chips and Solderpaste <--- how does that sounds for a restaurant name? ;)
<rqou> lolol
<azonenberg_work> jn__: looool
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<pie_> boxes for light switches?
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<m_w> cr1901_modern: I ported the SDRAM code to Beaglewire but ran out of SRAM for litex
<m_w> is there a way to lighten the SRAM requirements?
<m_w> even lite-er-x
<m_w> using picorv32 as the core was the closest to fitting
<cr1901_modern> m_w: Any chance you could upload a zip of the failing design or something?
<m_w> I can do a diff
<m_w> there were also some warnings that I didn't like
<m_w> a divide by zero thing, I think the code wasn't considering a 8 bit data bus in it calculations
<m_w> lemme see waht I can post
<m_w> *what
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<cr1901_modern> m_w_: You are _probably_ running out of SRAM due to CPU RAM (yes, even if you have DRAM, SRAM will be allocated) and ROM being allocated inside the block RAM
<cr1901_modern> inside the FPGA* as block RAM
<m_w_> ./beaglewire.py --no-compile-software --integrated-rom-size 32 --cpu-type picorv32
<m_w_> yeah I looked at the generated code
<cr1901_modern> 32 kB?!
* azonenberg_work has some FPGA designs that have used upward of a megabyte of block ram
<m_w_> just an example of the input I was trying
<m_w_> fatal error: failed to place: placed 32 RAMs of 40 / 32
<m_w_> just not enough RAM in the ICE40 to handle litex
<cr1901_modern> m_w_: I want to see the emitted verilog code in a pastebin
<m_w_> cr1901_modern: sure
<cr1901_modern> I don't actually remember the units "integrated-*-size" uses
<rqou> offtopic: i just had to help the person next to me get a C/C++ library installed and linked properly
<rqou> i never realized just how much this problem wastes people's time
<m_w_> I think it was bytes
<cr1901_modern> m_w_: Yes it's bytes, and I think I see the problem
<m_w_> not enough SRAM :)
<cr1901_modern> Yes, but... try: l2_size=0
<cr1901_modern> If you're going to want this to fit, you're going to have tradeoffs
<m_w_> large tag mem and data_mem
<m_w_> of course
<m_w_> lets try it
<m_w_> cr1901_modern: where do I add that parameter?
<cr1901_modern> To the SoCSDRAM __init__ input arguments
<m_w_> raise TypeError("Width must be a strictly positive integer")
<cr1901_modern> Of course, despite the fact there's a check for l2_size being 0 here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L74
<m_w_> switched it to l2_size=32 and ....
<m_w_> fatal error: failed to place: placed 6002 LCs of 7575 / 7680
<m_w_> pricked the pnr
<cr1901_modern> _florent_: How do you disable l2 cache on a SocSDRAM?
<m_w> *bricked
<cr1901_modern> m_w_: Sorry, right now I have to attend to other things :/
<m_w> no biggie
<m_w> just wanted to give a status update before I forgot about it
<cr1901_modern> The immediate problem is the l2 cache. Idk why the usage exploded w/ l2_size=32. Maybe yosys decided to not map it to bram anymore and use LUTs directly
<cr1901_modern> (but that's a _huge_ amount of LUTs)
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<m_w> yeah I will poke at it later now that I know of the l2 parameter