00:05
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00:26
<
whitequark >
digshadow: nope.
00:26
<
whitequark >
you could probably do it with grep.
00:32
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00:33
<
digshadow >
whitequark: with some knowledge of the bitstream internals?
00:33
<
digshadow >
I don't remember seeing resource utilization in there, but can double check
00:35
<
awygle >
on further reflection it seems like you should be able to get what you want from yosys, no? at least in terms of "how many LEs are being used". it seems unlikely that icebox/icestorm could tell you any more except possibly how many resources your particular part number has.
00:36
<
awygle >
i guess if you only have the .asc you need to run it through icebox_vlog to feed it to yosys
00:38
<
whitequark >
awygle: it's kind of weird but yosys doesn't have resource utilization stats for any of the targets
00:38
<
whitequark >
that's reasonable to some degree because e.g. gp4par can fold LUTs into inverters and back
00:38
<
digshadow >
awygle: I'm not only using yosys
00:38
<
digshadow >
but also would be better to be sure that nothing funny happened
00:38
<
awygle >
whitequark: but will it tell you "i synthesized 9436 of this cell"?
00:39
<
whitequark >
i think it does yeah
00:39
<
whitequark >
but you can also just use grep for that
00:39
<
awygle >
that's the best you're going to get until you run arachne, i think
00:39
<
whitequark >
digshadow: `grep -c SB_LUT4 bitstream.asc`?
00:39
<
awygle >
(or gp4par or xc2par or whatever)
00:39
<
whitequark >
er, wait, asc
00:39
<
whitequark >
hang on
00:40
<
digshadow >
whitequark: it looks like I could look for all 0 sections
00:40
<
whitequark >
ok yeah don't know about an asc, I thought you had a blif
00:40
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00:40
<
whitequark >
so I have a floorplan viewer (unreleased) that can open an asc
00:41
<
digshadow >
ah cool
00:41
<
whitequark >
I can whip up a resource utilization page for it real quick if you wanna
00:41
<
whitequark >
can you give me the bitstream for testing
00:41
<
digshadow >
hmm CLI tool would be useful
00:41
<
digshadow >
I'm comparing a bunch of tools
00:41
<
whitequark >
well I can make it CLI I guess
00:41
<
mithro >
digshadow: Try iceexplain ?
00:41
<
awygle >
this should be a really easy add to icebox
00:41
<
digshadow >
mithro: not familiar with that, let me look
00:41
<
whitequark >
yeah but I'm not motivated to do that :p
00:41
<
awygle >
:p fair enough
00:41
<
whitequark >
icebox_explain doesn't really give you resource util
00:41
<
mithro >
icebox_explain ?
00:42
<
whitequark >
digshadow: nevermind
00:42
<
whitequark >
icebox_stat does what you want
00:42
<
whitequark >
icebox_stat file.asc
00:42
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00:44
<
digshadow >
whitequark: perfect! thanks
00:49
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01:18
<
digshadow >
I don't see a --version flag on any of the icebox tools. Is there a way to query from an installed instance something resembling a version?
01:20
<
digshadow >
also note icebox_asc2hlc.py has a --version but it actually outputs copyright info, not version info
01:22
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01:24
<
whitequark >
I don't think there is
01:24
<
whitequark >
icebox is kind of hacky
01:25
<
mithro >
digshadow: Can you get the "git describe"?
01:25
<
digshadow >
mithro: not from an installed instance
01:29
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01:30
<
tinyfpga >
mithro: I’ll add a link to the pictures :)
01:31
<
mithro >
tinyfpga: Anywhere on that column would be nice :-P
01:31
<
mithro >
tinyfpga: Would be good to have a TinyFPGA B2 link somewhere too?
01:33
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02:07
<
mithro >
Does anyone understand what padin_1 / padin_0 is all about?
02:08
<
mithro >
Looks like it might have something to do with the in built oscillators?
02:08
<
mithro >
The <span style="font-family:monospace">CLKHF</span> output of SB_HFOSC is connected to both IPConnect tile (0, 28) output <span style="font-family:monospace">slf_op_7</span> and to the <span style="font-family:monospace">padin</span>
02:09
<
mithro >
icebox/icebox.py: (1, 331, 143): ("padin_glb_netwk", "3"), # (1 3) (331 144) (331 144) routing T_0_0.padin_3 <X> T_0_0.glb_netwk_3
02:12
<
mithro >
Looks like it can be used to connect io_X/PAD to padin_X which is an alias for a glb_network_Y ?
02:34
<
awygle >
mithro: each iob has 2 pads, and so can connect to 0 1 or 2 pins. Is that what you mean?
02:35
<
awygle >
Io tile, io cell, whatever ice calls it
02:37
<
mithro >
So a bunch of IO tiles can drive the global networks -- if an IO tile can drive a global network, then the fabout is connected to one global network and the GLOBAL_BUFFER_OUTPUT (direct from the PACKAGE_PIN) can drive a another specific global network
02:38
<
mithro >
I don't quite understand where padin_x comes in there...
02:47
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02:53
<
pie_ >
rqou, so you figure out your dump?
03:12
<
rqou >
pie_: right mux index 0 kinda makes sense?
03:13
<
rqou >
it'd be really helpful if you could figure out how the row index permutation works
03:27
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04:55
<
rqou >
azonenberg: ping?
05:14
<
azonenberg >
rqou: ack
05:15
<
rqou >
can you take some guesses as to wtf is going on with the horizontal pin permuting?
05:15
<
rqou >
i don't think you need too much uarch understanding for this, just good pattern-recognition skills
05:16
<
rqou >
alternately, any thoughts as to what should be analyzed next?
05:35
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06:08
<
rqou >
hmm, so far there is very limited connectivity between differently-numbered wires
06:20
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07:11
<
daveshah >
mithro: still around?
07:11
<
mithro >
daveshah: ha
07:11
<
mithro >
daveshah: I was just about to ping you
07:12
<
mithro >
daveshah: Do you know anything about the blockrams in the 8k?
07:12
<
daveshah >
The main thing is that various signals swap tiles
07:14
<
daveshah >
I think LSB/MSB and read/write address/clock swap round
07:14
<
daveshah >
But you can check by seeing exactly which signals are in the database for each tile
07:14
<
mithro >
daveshah: "The cell ports are spread out over the two tiles as follows:" is wrong? It's dependent on which RAMB/RAMT column?
07:15
<
mithro >
daveshah: That is what I'm discovering
07:15
<
daveshah >
No, its dependent on 1k/8k
07:15
<
daveshah >
As above
07:15
<
mithro >
DEBUG:root:On PI( 8,13) skipping entry [!B4[0],B4[1],!B5[0],B5[1] buffer local_g0_2 ram/RCLKE]: dst missing PV(10,15):local_g0_2 (local_g0_2) node X010Y015<|07|>X010Y015 =>
*PV(10,15):ram/RCLKE* (ram/RCLKE) node None
07:15
<
mithro >
daveshah: Hrm? You mean the 8k and 1k have different ordering?
07:16
<
daveshah >
The RAMs are quite different between the two. The config bits change meaning too
07:16
<
mithro >
daveshah: So that page should really say "In the 1k, the cell ports are spread out over the two tiles as follows:" ....
07:16
<
daveshah >
I think all wires swap between the two tiles from 1k to 8k
07:17
<
daveshah >
Everything subsequent, like the 5k, is the same as the 8k
07:19
<
daveshah >
BTW the padin signals are the connections from the pad just before the global network itself
07:19
<
daveshah >
The connection from them to the global network is enabled by an extra config bit
07:19
<
daveshah >
By default fabout is routed to the global network
07:21
<
mithro >
daveshah: Is there a way in icebox to look up a ram tile signal name (IE ram/RADDR_0 ram/RE) and find out if that is in a RAMB or RAMT tile?
07:22
<
daveshah >
mithro: probably, but I think you can just say that they all swap over going from 1k to 8k
07:23
<
daveshah >
I think that will be easier in fact
07:41
<
whitequark >
mithro: what are you doing btw?
07:41
<
mithro >
whitequark: Getting ice40 into vpr
07:42
<
mithro >
whitequark: For timing driven PnR -- blinky is working on the 1k + icestick
07:46
<
mithro >
Most of my time is being spent finding issues in the ice40 documentation :-P
07:48
<
mithro >
daveshah: So GLOBAL_BUFFER_OUTPUT is actually connected/disconnected to padin_X which is shorted to a global network?
07:49
<
daveshah >
Yes, so long as the padin_pio config bit is set
07:51
<
daveshah >
Otherwise the SB_GB driven from fabout is connected to the global network
07:51
<
rqou >
hey whitequark are you good at puzzles/patterns?
07:52
<
mithro >
daveshah: so you can't drive both the fabout and padin_X global networks at the same time?
07:52
<
whitequark >
rqou: no i hate them
07:53
<
daveshah >
mithro: No, of course not - that would be a short circuit
07:53
<
daveshah >
But you can use both padin and fabout at the same location, because they drive different networks
07:53
<
whitequark >
mithro: please document all the issues somewhere
07:53
<
whitequark >
in any way
07:54
<
mithro >
daveshah: Not sure what you mean by "<daveshah> mithro: No, of course not - that would be a short circuit"?
07:54
<
daveshah >
mithro: two drivers for the same net is clearly a short circuit
07:55
<
mithro >
daveshah: but the fabout and padin_X are driving different networks?
07:55
<
daveshah >
whitequark: docs have been updated for the biggest problem found (actually we found it during $thing_on_cliffords_twitter)
07:55
<
daveshah >
The routing muxes actually be unidirectional
07:55
<
daveshah >
mithro: yes, you can use fabout and padin at the same location
07:55
<
daveshah >
So long as each glb_netwk only has one driver
07:56
<
whitequark >
mithro: btw any interest in ice40 floorplan viewer?
07:56
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07:56
<
whitequark >
I wrote one with Qt, it works way better than this other thing in html
07:57
<
mithro >
whitequark: Oh?
07:57
<
rqou >
but now you have to deal with qt
07:57
<
daveshah >
whitequark: we are working on something like that too, more information at the end of the month
07:57
<
whitequark >
daveshah: shit
07:57
<
daveshah >
Coincidentally also using Qt+OpenGL
07:57
<
whitequark >
why the fuck is this secrecy happening?
07:57
<
daveshah >
But it is not designed to take a bitstream in, so it's not quite the same
07:57
<
rqou >
yeah, this is what happens when symbiflow claims to be doing foss
07:58
<
whitequark >
"more info wherever" more info now
07:58
<
whitequark >
or this isn't open-source
07:58
<
daveshah >
Go and pester clifford, not my decision
07:58
<
rqou >
symbiflow is doing foss, corporate/academic edition
07:58
<
rqou >
so no, not foss
07:59
<
rqou >
needs a makefile?
07:59
<
daveshah >
Some of it is open source...
07:59
<
rqou >
twitter teasing is not foss either
08:00
<
whitequark >
rqou: qmake .; make
08:00
<
rqou >
lesson: don't have your project be sponsored by $BIG_COMPANY
08:00
<
daveshah >
Tbh that's not really why it's not open source yet
08:01
<
whitequark >
there's no routing pushed yet because i still don't have a non-ugly rendering for it, but i think i know how to do it, finally
08:01
<
daveshah >
whitequark: looks awesome (much better than what we have right now)
08:01
<
whitequark >
daveshah: join forces?
08:01
<
rqou >
whitequark: missing a -std=c++11 somewhere
08:02
<
rqou >
getting errors about std::function
08:02
<
whitequark >
rqou: starts with CONFIG += c++11
08:02
<
whitequark >
are you building with qt4 or qt5?
08:02
<
rqou >
g++ -c -m64 -pipe -O2 -Wall -W -D_REENTRANT -DQT_DEPRECATED_WARNINGS -DQT_NO_DEBUG -DQT_GUI_LIB -DQT_CORE_LIB -DQT_SHARED -I/usr/share/qt4/mkspecs/linux-g++-64 -I. -I/usr/include/qt4/QtCore -I/usr/include/qt4/QtGui -I/usr/include/qt4 -I. -I. -o main.o main.cpp
08:02
<
mithro >
rqou: says mister <redacted>
08:02
<
whitequark >
i'm not sure if it even works with qt4, try qt5-qmake
08:02
<
rqou >
<redacted> is not related to the open-source FPGA efforts
08:03
<
mithro >
whitequark: what is that displaying?
08:03
<
whitequark >
mithro: one logic slice on an ice40-384 fpga
08:03
<
whitequark >
i correctly decode everything on logic tiles other than local tracks and span wires
08:04
<
whitequark >
for luts i infer the function from the lut bits
08:04
<
mithro >
whitequark: I mean, C+D is describing a LUT?
08:04
<
whitequark >
mithro: yes
08:04
<
whitequark >
there's another mode that displays LUT as raw bits or a different way to render logic function
08:05
<
mithro >
whitequark: So A/B on those LUTs are unused?
08:05
<
rqou >
whitequark: which -dev packages do i need to install?
08:05
<
whitequark >
rqou: ugh let me just write a README
08:10
<
whitequark >
rqou: ok nope it doesn't work with qt 4
08:15
<
rqou >
mithro: anyways, project chibi has nothing redacted
08:15
<
rqou >
the redacted projects are not open fpga projects
08:16
<
rqou >
whitequark: so i installed qt5-qmake
08:16
<
rqou >
it installs a binary x86_64-linux-gnu-qmake
08:16
<
rqou >
when i run it the -std=c++11 is passed
08:16
<
rqou >
and then it complains that there's no QApplication include
08:16
<
rqou >
so i need a -dev package of some kind?
08:17
<
daveshah >
rqou: nothing has ever been redacted in Trellis either, I agree with that on a personal level
08:17
<
daveshah >
Just there are other constraints, just sorting out things like copyright and stuff properly, for bigger projects
08:18
<
daveshah >
I promise there's nothing more sinister than that going on anywhere in SymbiFlow
08:18
<
rqou >
that's not what i've been hearing
08:19
<
whitequark >
rqou: done
08:19
<
rqou >
oh wtf it doesn't start with lib
08:19
<
rqou >
no wonder i couldn't find it
08:20
<
rqou >
huh, why didn't i have this installed before, that's interesting
08:20
<
openfpga-github >
icefloorplan/master 0dc1e7a whitequark: Fix dead links in README.
08:20
<
rqou >
ok, now it's building
08:20
<
rqou >
shoulda made it a web thing
08:21
<
whitequark >
rqou: qt5 compiles to wasm
08:21
<
whitequark >
so i -could- make it a web thing
08:21
<
rqou >
O_o it does?
08:21
<
rqou >
with accelerated rendering?
08:21
<
whitequark >
how else
08:21
<
rqou >
there was a very very early qt emscripten demo that was slow as shit
08:21
<
whitequark >
it's even "only" 4M
08:22
<
whitequark >
qt5 doesn't render without gl
08:22
<
whitequark >
the entire stack uses gl
08:22
<
whitequark >
specific widgets not necessarily
08:22
<
whitequark >
fun fact: i actually render the floorplan -without- gl specifically, because antialiasing in gl is shit
08:22
<
rqou >
um, how do i do anything? :P
08:22
<
whitequark >
qt optimizes the hell out of software rasterization so it's pretty much just as fast
08:23
<
whitequark >
see README
08:23
<
rqou >
right, the demo that still gets linked was qt4 i think?
08:23
<
whitequark >
qt4 is so 2010s
08:23
<
rqou >
anyways, it was a giant hack compiled with a very early emscripten
08:23
<
whitequark >
er, 2000s
08:24
<
rqou >
wtf "use gl mode" looks way worse than normal
08:24
<
whitequark >
exactly
08:25
<
whitequark >
try opening more complex bitstreams
08:25
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08:25
<
whitequark >
also hover nets
08:25
<
rqou >
yeah i'm opening my saturn cdb dumper hack thing
08:25
<
whitequark >
it may not have routing but it associates symbols with nets already :p
08:26
<
rqou >
wow this is really really good
08:26
<
rqou >
can you make me one for max v when project chibi is done?
08:26
<
whitequark >
sure why not
08:26
<
rqou >
er, ram/io aren't shown are they?
08:26
<
whitequark >
i didn't do ram/io drawing code yet
08:27
<
whitequark >
spent like three weeks so depressed i was pretty much catatonic
08:27
<
whitequark >
tends to prevent software development
08:27
<
whitequark >
well, fortunately mirtazapine seems to work pretty well
08:27
<
rqou >
hope you feel better now
08:27
<
whitequark >
about as well as clomipramine but i can actually stand up without fainting and walk more than three meters in a line
08:27
<
rqou >
oh final note, i have to use x86_64-linux-gnu-qmake rather than qmake
08:27
<
rqou >
qmake is still the qt4 version
08:28
<
rqou >
maybe i need to mess around with debian alternatives?
08:28
<
whitequark >
debian whatever has qt5 qmake as qmake
08:28
<
whitequark >
buster?
08:28
<
whitequark >
testing.
08:28
<
rqou >
um, i'm on a somewhat-outdated sid
08:28
<
rqou >
maybe that's the issue
08:28
<
rqou >
did they flip it recently?
08:29
<
whitequark >
not a clue
08:29
<
whitequark >
debian does weird shit constantly
08:29
<
rqou >
i know right?
08:29
<
whitequark >
i trust they usually have a good reason but god damn it
08:29
<
whitequark >
how hard can it be to put some linux binaries in tarballs
08:29
<
whitequark >
(narrator: hardest problem in computing)
08:30
<
rqou >
well, i'm still on a slightly franken-debian because some newer packages broke things and i haven't had time to fix them
08:30
<
q3k >
whitequark | fun fact: i actually render the floorplan -without- gl specifically, because antialiasing in gl is shit
08:30
<
q3k >
what do you mean?
08:30
<
q3k >
you MSAA and it works? (tm)
08:30
<
rqou >
i should probably deal with the problems soon since apparently debian is nearing a release or something?
08:31
<
q3k >
or do you mean GL_LINES?
08:31
<
q3k >
(fuck GL_LINES)
08:31
<
rqou >
and the version skew is probably not good
08:31
<
mithro >
whitequark: How do I zoom?
08:31
<
whitequark >
q3k: whatever qt does when rendering to gl doesn't look nice
08:31
<
q3k >
whitequark: hum
08:31
<
whitequark >
mithro: see README
08:31
<
q3k >
whitequark: works for me, literally
08:31
<
q3k >
wrote Qt5 GL code... yesterday
08:32
<
whitequark >
seriously, does anyone read that shit
08:32
<
q3k >
looks fine on all the graphics cards I've tested
08:32
<
whitequark >
whom did i write it for lol
08:32
<
rqou >
the "Ctrl" part isn't emphasized enough
08:32
<
whitequark >
q3k: can you clone and take a look at what i'm doing wrong
08:32
<
rqou >
it doesn't behave like any "cad/eda/graphics" tool i've ever used
08:32
<
whitequark >
rqou: without Ctrl it interacts badly with touchpads that have horz/vert scroll
08:33
<
rqou >
ooh you mean touchpads that still use oldschool "edge" scrolling?
08:33
<
rqou >
rather than two-finger?
08:34
<
whitequark >
rqou: nope
08:34
<
whitequark >
i have two-finger 2d scrolling
08:34
<
mithro >
whitequark: What does the "compact logic notation" mean?
08:34
<
rqou >
hmm, never had problems with that, but whatever
08:34
<
whitequark >
mithro: try it
08:35
<
rqou >
can you make it an option?
08:35
<
rqou >
also, can i get middle-mouse-button panning?
08:35
<
mithro >
whitequark: Yes, I don't understand why its "=1"?
08:36
<
whitequark >
mithro: "exactly one bit is 1"
08:36
<
whitequark >
ie xor
08:36
<
whitequark >
">=1" is or
08:37
<
whitequark >
rqou: patches welcome? :p
08:37
<
whitequark >
i don't really have a middle mouse button here
08:37
* mithro
wants +/- keys for zooming :-)
08:37
<
daveshah >
mithro: I think is is basically the IEEE standard?
08:37
<
whitequark >
yeah ^
08:42
<
rqou >
wait there's an ieee standard for how to write logic equations?
08:42
<
daveshah >
rqou: surely you did it at uni?
08:43
<
daveshah >
Classic first year EE, at least in the UK
08:43
<
daveshah >
Symbols, not equations
08:43
<
rqou >
just ad-hoc DNF
08:43
<
whitequark >
mithro: wish granted
08:44
<
rqou >
ooh
_those_ symbols
08:44
<
openfpga-github >
icefloorplan/master 99eac4c whitequark: Bind zoom on +/- buttons.
08:44
* rqou
just checked wikipedia
08:44
<
rqou >
yeah, we just used the "distinctive shape" forms
08:44
<
daveshah >
We did mostly too, but also the IEEE ones
08:45
<
rqou >
i don't think i've ever seen anybody use the IEEE ones
08:45
<
daveshah >
We also spent quite some time discussing how the use the IEEE standard to build symbols for more complex gates
08:45
<
rqou >
we never did that
08:45
<
daveshah >
Very useful to the bulk of students going on to work in companies building systems out of assorted 74-series MSI logic :P
08:46
<
whitequark >
i thought about doing distinctive shapes but decided i'm lazy
08:46
<
whitequark >
and they aren't very useful for 4-luts anyway
08:46
<
daveshah >
Yeah, most of the time post synthesis stuff ends up being some weird function or other
08:47
<
daveshah >
Being able to detect full adders, in combination with carry logic, would be neat
08:47
<
rqou >
oh, you mean "what azonenberg was asked to research before ioa put him on projects that actually earn money"
08:47
<
rqou >
aka "clifford can't make extract_fa work"
08:48
<
rqou >
although i can't really complain because i couldn't find the bug either
08:48
<
whitequark >
daveshah: I detect full adders
08:48
<
whitequark >
in icefloorplan
08:48
<
daveshah >
whitequark: oh, even more awesome
08:48
<
whitequark >
it says ∑ for those
08:48
<
whitequark >
there's only really one encoding for a full adder with the ice40 layout so it was easy
08:49
<
whitequark >
you know the really funny thing?
08:49
<
whitequark >
that other floorplan viewer did logic function recognition by building a 65536 element map
08:49
<
whitequark >
bruteforcing it basically
08:49
<
whitequark >
i... wrote a oneline condition for every function
08:49
<
whitequark >
i spent longer second-guessing whether i'm missing something than writing it
08:49
<
rqou >
hmm, i think azonenberg's RE project can be improved by doing some early passes
_before_ untechmapping
08:52
<
whitequark >
rqou: no but seriously, can you just implement that so i don't have to find a mouse
08:53
<
rqou >
i've never worked with qt
08:53
<
rqou >
currently doing something else
08:53
<
whitequark >
alright then i'll uhh. let's see
09:03
<
whitequark >
rqou: i copied the top answer from stackoverflow :P
09:03
<
openfpga-github >
icefloorplan/master 8e71c22 whitequark: Allow panning with middle mouse button....
09:05
<
whitequark >
pester me if you want routing badly
09:05
<
whitequark >
i got myself nerdsniped by Coq, kinda
09:07
<
rqou >
ugh the max v interconnect is full of strange not-quite-identical patterns
09:07
<
rqou >
i should just decap one
09:11
<
daveshah >
whitequark: icefloorplan built with no trouble on Arch and works well for a picosoc test even without OpenGL. But I do notice occasionally zooming out too far causes it to flip
09:12
<
whitequark >
daveshah: flip?
09:13
<
whitequark >
lol wtf
09:14
<
whitequark >
literally flip
09:14
<
whitequark >
i'll uh... fix that
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09:48
<
mithro >
How did it get 2:47 am!?
10:47
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15:48
<
awygle >
ctrl+scroll is the most intuitive binding for zoom, fite me
15:50
<
qu1j0t3 >
sure, at a pinch
15:50
<
cr1901_modern >
I too prefer ctrl+scroll for zoom. shift-scroll for horizontal pan. scroll for vertical pan. Like inkscape does it
15:51
<
cr1901_modern >
(pinch? of course you wouldn't use inkscape on a touchscreen :)...)
15:52
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15:55
<
awygle >
I like click and drag panning. But I prefer right click or control click rather than middle mouse like kicad
15:57
<
Ultrasauce >
my colleague has one of those mice with no detentes in the scroll wheel
15:57
<
Ultrasauce >
zooming can get kind of scary
15:59
<
qu1j0t3 >
i have an Apple mouse with the little rubber nipple, i.e. it never works properly for scrolling
16:04
<
awygle >
Altium does this thing where if you hold middle click it freezes the cursor in place and then zooms in when you move the mouse up and out when you move down
16:04
<
awygle >
It's extremely weird but I definitely find myself using it
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17:38
<
pb_ >
rqou: surprise-surprise, quartus names are related to interconnect permutations.
17:38
<
pb_ >
you may want to look for patterns with them. also, it maybe time to look at name mapping for bigger chips.
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18:57
<
rqou >
i'm still missing LE->fabric connections
18:58
<
rqou >
the bottommost one goes into the row below, but the topmost one also goes into the row above
20:59
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21:58
<
awygle >
daveshah: ping?
21:58
<
daveshah >
awygle: pong (but midnight now and I'm tired, only around for a few more mins)
21:58
* awygle
sort of regrets missing the "u up" joke
21:59
<
awygle >
daveshah: on the ice40 UP, do you know whether CDONE can be configured as a user I/O?
21:59
<
daveshah >
awygle: only in the wlscp30 package
21:59
<
awygle >
specifically in the QFN - it's pretty clear that the WLCSP can do so
21:59
<
awygle >
awesome, thanks
21:59
<
daveshah >
No, no evidence that its possible in the QFN
21:59
<
daveshah >
I think in the WLCSP they just connect one of the IO not used in that package to the same pad
22:00
<
awygle >
is CDONE open drain? or push pull?
22:00
<
daveshah >
Open drain
22:00
<
daveshah >
Low during config, then floating
22:00
<
awygle >
sweet. thanks again, sleep well etc
22:01
<
daveshah >
Thanks, good luck with the Glasgow work
22:01
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22:10
<
awygle >
ugh why don't vendors publish footprints. why is that so hard.
22:12
<
rqou >
you know, i do occasionally think about how it's amazing any engineering every can get done
22:14
<
awygle >
yeah the more i learn about engineering the more i'm of two minds
22:14
<
awygle >
one is "we took sand and made the internet, that's fucking amazing"
22:14
<
awygle >
the other is "i'm terrified of cars and bridges and elevators now"
22:15
<
rqou >
at least supposedly civil infrastructure was built with much more serious/for-realz design practices
22:15
<
rqou >
and not the internet's "worse is better"
22:16
<
awygle >
that's what i hear
22:16
<
awygle >
but i literally can't imagine what that looks like
22:16
<
qu1j0t3 >
i am increasingly concerned that this stuff doesn't survive generational transfer.
22:17
<
qu1j0t3 >
we keep having to pull people out of retirement to figure stuff out.
22:17
<
qu1j0t3 >
that has a time limit.
22:17
<
awygle >
i'm not totally sure what you're referring to
22:17
<
qu1j0t3 >
just a bunch of things been observing in recent years
22:17
<
qu1j0t3 >
incl ageism
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23:10
<
rqou >
hrm, the column ios really are worse than the row ios in a lot of ways
23:10
<
rqou >
there's no path from lab outputs to the column io local interconnect
23:10
<
rqou >
just the hacked-on fast path
23:11
<
rqou >
afaik there's no fast input either
23:15
<
rqou >
the left and right ios are also not identical?!