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<rqou> I love how my <redacted> has four different footprint silkscreen styles thanks to symbols being stolen from four different places
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<rqou> O_o rust shipped simd support
<rqou> i guess they really haven't been slacking and feature after feature is starting to land
<mithro> tinyfpga: Why is the clock on B4 on the TinyFPGA B2? That doesn't seem to be a global net driver on the ice40 8k?
<cr1901_modern> >awygle: berenstein bears
<cr1901_modern> For the love of all that is holy, don't even start ._.
<tinyfpga> mithro: it’s also connected to C4...that connects to a global buffer
<tinyfpga> mithro: I think I just wasn’t paying attention when I made the pin constraint file
<mithro> tinyfpga: digshadow grabbed the info from your example -- so maybe that should be changed?
<tinyfpga> mithro: yes, I need to change the example
<tinyfpga> mithro: but I didn’t connect it to a global buffer in the BX at all
<mithro> tinyfpga: oh? that's less than ideal :-(
<tinyfpga> mithro: I probably should have...but I don’t think it will be a huge issue
<tinyfpga> mithro: yeah, not ideal
<tinyfpga> mithro: I can connect it to a global
<tinyfpga> mithro: ...buffer in the next production run in the fall
<mithro> digshadow was just testing the ice40 8k in vpr -- but I'm still in the process of adding support for routing onto the global buffers from the fabric
<tinyfpga> mithro: ohh, I see XD
<mithro> tinyfpga: It generated the design correctly but failed because the clock signal wasn't on a global buffer driving pin
<tinyfpga> mithro: you should be fine on the B2 then if you use C4 for the clk
<tinyfpga> That’s global buffer 0
<mithro> yeap, John is going to test that tomorrow
<tinyfpga> woohoo!
<tinyfpga> Send me a tweet when you have it working
<tinyfpga> I mean...tweet it to everyone XD
<mithro> tinyfpga: When I have a picorv32 working is when I'll tweet
<mithro> I think elms is pretty close to getting RAM working
<tinyfpga> ok
<mithro> Had blinky working fine on the icestick :-)
<tinyfpga> nice!
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<mithro> vpr is much slower than arachne -- it takes a like a _whole_ 5 seconds to do the flow but it does get a much better result
<rqou> hmm, this fuzzer has a problem
<rqou> 10k routes not working due to fuzzer sucking
<rqou> i guess this is what happens if your naive router cannot ripup existing routes
<rqou> ok, maybe fixed it
<rqou> nope
<rqou> ok, applied a different hack
<rqou> very high quality code all around
<rqou> also, idempotent code is good
<rqou> whee, surpassed 100k "doesn't work" paths
<rqou> ok, yet another hackfix
<rqou> if only somebody had written an actually good "worse is better" P&R tool *hint* *hint*
<rqou> hey azonenberg: ping?
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<rqou> alright, fuzzing should be complete except for three entries that for some reason the automated tool is choking on
<rqou> i can probably do those manually
<rqou> and then i think it's analysis time?
<rqou> no wait
<rqou> there's still some missing information about the left/right IOs trying to enter the fabric
<azonenberg> Back
<rqou> what were you doing? house?
<azonenberg> Yeah
<rqou> how's it going?
<azonenberg> Didnt get a ton done since i was in the city for work today and the boat back to seattle was delayed for some reason
<azonenberg> We cut out trim boards for a window, then bought some more supplies
<azonenberg> hung the exterior lights on the garage and by the front door and caulked around them
<azonenberg> moved the rest of one pallet of insulation inside
<azonenberg> And tarped the other 4 pallets since it was cloudy and we didnt want them to get wet if it rained
<azonenberg> and it was too late to keep working
<azonenberg> Tomorrow i'm working remote so we should get a good 4-5 hours of work in
<rqou> why does it always sound like you have a giant mile of "misc" left no matter what?
<azonenberg> Because building a house is a massive project :p
<azonenberg> Tomorrow's goal is to hang the last exterior light (on the back deck), install the power outlet on the back deck
<azonenberg> finish doing trim on all of the windows with normal sills
<azonenberg> then probably start thinking about getting plywood pieces for the office window and a few other spots that need deeper cavities
<azonenberg> oh, and i think we still need firestop foam around a few cable penetrations
<rqou> WTF dude
<rqou> why so much stuff?
<azonenberg> well, it didnt get done earlier :p
<azonenberg> The rough-in inspection just involves putting electrical boxes up
<azonenberg> and wiring
<azonenberg> not any of the fixtures
<azonenberg> in fact you arent allowed to do fixtures earlier, as the inspector has to be able to look into the boxes
<rqou> seems like you keep getting bottlenecked on inspection
<azonenberg> not really
<rqou> something something small government become a republican :P :P :P :P :P
<azonenberg> We've never been in a situation where we had nothing to do until an inspector came
<azonenberg> While waiting for the electrical inspector, we were caulking things
<azonenberg> While waiting for the caulking inspection, we'll be finishing framing
<azonenberg> Some tasks, like hanging insulation, are indeed blocked pending inspection of other things
<azonenberg> but that doesnt mean we have nothing to do
<azonenberg> If we ever run out of things to do there's a bunch of interior electrical finish work to do
<azonenberg> Two now-unused boxes need to have covers installed, then i have to install the kitchen, laundry room, and both bathroom light fixtures (rewired, but the sheetrock is up so no reason we can't do those fixtures now)
<azonenberg> plus the bathroom power receptacles
<azonenberg> that can happen at any time before the final electrical inspection
<azonenberg> i'm keeping that work in reserve if i ever have nothing to do
<rqou> so anyways, the actual question
<rqou> azonenberg: thoughts on having a "worse is better" coolrunner-ii toolchain for microcontrollers or whatever?
<rqou> or should i just make xc2bit no_std compatible?
<azonenberg> Dont know
<rqou> do you care about this use case?
<azonenberg> I see it as being potentially useful but i have no immediate use for it
<azonenberg> I would say, dont put any effort into it either way at this time
<azonenberg> until there's a user request for it
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<rqou> ok, pretty sure the things the tool can't figure out are not connected
<rqou> anyways, now the only fuzzing that still isn't quite done is left/right IOs
<rqou> azonenberg: time to apply more brain now?
<rqou> azonenberg: the muxes are in general not as fully utilized as i would expect
<rqou> 15513 sources among 1696 muxes
<rqou> so a bit more than 9 per mux on average
<azonenberg> interesting
<rqou> azonenberg: ok, somehow the rightmost column is special somehow
<rqou> both the "L" and "second set of L" wires have config bits mirrored horizontally
<rqou> but "second set of L" wires logically occupy the spots that would normally be used by R wires which are not mirrored
<rqou> (i'm treating the R0-3 wire bit configuration as the "canonical" one)
<rqou> and the U/D wires are weird too somehow
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<azonenberg> Unsurprising, if it's a boundary location
<pie__> if openfpga ever gets a tv series, it could be a running gag that azonenberg keeps knocking down and rebuilding the same wall just to seem busy
<azonenberg> pie__: :p
<pie__> ;D
<azonenberg> one way or another this remodel is going to be over at the end of next month
<azonenberg> Because thats when my landlord kicks me out :p
<azonenberg> I mean i have longer time horizon projects too, like the kitchen and bathrooms
<azonenberg> but those will be done while living in the house
<rqou> i'm amazed your wife is ok with that
<pie__> no need to cook for a while :p , assuming she does
<pie__> which is actually probably less fun for everyone
<pie__> cold food :'(
<pie__> also something about :D
<rqou> ok, the rightmost column is really really special
<pie__> rqou, give it a cute sticker
<rqou> wat
<pie__> well you said its special
<pie__> sigh i should just go back to sleep :p
<rqou> fine, i can give it a ⑨ sticker
<pie__> meanwhile watering_can_eating_things.avi
<rqou> wat
<rqou> you need to meme less
<pie__> it's all deeply allegorical
<azonenberg> pie__: house of theseus? :p
<azonenberg> We're keeping all of the structural components intact
<azonenberg> And basically all the plumbing
<pie__> yeah i figured
<pie__> otherwis you would have literally built a house
<azonenberg> well, we also didnt realize half this stuff had to be done when we bought it
<azonenberg> we wanted to keep the old insulation
<azonenberg> But a) it reeked and b) it wasn't a high enough R-value to be legal to keep
<azonenberg> and c) a bunch of the vapor barrier was damaged when we removed the drywall
<azonenberg> But by the time we got to that point we largely knew we weren't keeping it
<pie__> yeah, life happens i guess
<rqou> so, who likes looking for patterns?
<pie__> feed to z3
<pie__> 3.???
<pie__> 4.prophet
<rqou> not sure that will work
<rqou> i think this requires some human brainpower
<pie__> well thats a lot of information to parse, or its very sparse
<pie__> not that you dont know that
<rqou> should be very repetitive somehow
<pie__> your eyes are probably attuned to it by now i presume buy X*Y*S*I* would be nicer to just read as a tuple?
<rqou> well, quartus does it this way
<rqou> also, some hints: X=1 and X=8 are IOs (and thus special)
<pie__> i want to muse about this but id just be bikeshedding since ive no idea how any of this works :(
<rqou> Y=0 and Y=5 are IOs, but a different kind
<pie__> "make a diagram"?
<rqou> there are some spreadsheets
<rqou> so azonenberg, wat do next?
<azonenberg> um
<rqou> needs some human brain at this point in time, no?
<azonenberg> yeah
<azonenberg> spend a while looking? :p
<rqou> azonenberg: so, what kind of assumptions might be safe to make?
<rqou> e.g. probably not safe to assume every tile is the same?
<azonenberg> definitely not, you've already proven that at least the interconnect varies
<rqou> aaargh
<rqou> i seem to be missing some fuzzing
<pie__> "use ML"
<rqou> because i was misled by the datasheet diagram
<azonenberg> lol
<rqou> "For R4 interconnects that
<rqou> neighbor can drive on to the interconnect."
<rqou> interconnect. For R4 interconnects that drive to the left, the primary LAB and its left
<rqou> drive to the right, the primary LAB and right neighbor can drive on to the
<rqou> that's definitely not what i observed
<pie__> time to figure out if your observation or the docs are broken woo :D
<rqou> no the docs are definitely broken
<rqou> so azonenberg, lesson for the future: altera docs are way more misleading than xilinx docs
<azonenberg> lol
<azonenberg> welp
<azonenberg> Xilinx docs in my experience are pretty accurate
<azonenberg> about uarch stuff
<azonenberg> they may have typos etc but not grossly factually inaccurate stuff
<rqou> so afaict the altera docs are still accurate
<pie__> kind of makes you wish there were names on them
<rqou> but only if you know _nothing low level at all_ about the uarch
<rqou> as soon as you know even a little bit you will be massively confused
<rqou> alternatively, it's all quartus's fault
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<pie__> is this the difference between programming model and actual impl?
<rqou> not sure?
<pie__> just wondering
<rqou> azonenberg: ping?
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<azonenberg> ack
<rqou> what do you think about this:
<rqou> ~~~~~ R: I0 ~~~~~
<rqou> | |0| | |0| | | | LE_BUFFER:X{x-1}Y{y}S0I1 ??? or IOs ???
<rqou> |0| | | | | | | | LE_BUFFER:X{x}Y{y}S0I0
<rqou> |G|C|D|H|A|B|E|F|
<rqou> | |0| | | |0| | | D:X{x}Y{y+1}I0
<rqou> | |0| | | | |0| | U:X{x}Y{y-4}I xxxx TODO IOs xxxx
<rqou> | |0| | | | | |0| R:X{x-4}Y{y}LogicalI0
<rqou> | | |0| |0| | | | U:X{x}Y{y-3}I0
<rqou> | | |0| | |0| | | D:X{x}Y{y+3}I0
<rqou> | | |0| | | |0| | D:X{x}Y{y+2}I0
<rqou> | | |0| | | | |0| L:X{x+1}Y{y}LogicalI8
<rqou> | | | |0|0| | | | R:X{x-2}Y{y}LogicalI0
<rqou> | | | |0| |0| | | wat
<rqou> | | | |0| | |0| | R:X{x-3}Y{y}LogicalI0
<rqou> | | | |0| | | |0| U:X{x}Y{y-2}I0
<azonenberg> cant really comment
<azonenberg> thats way beyond the level of uarch i know
<rqou> what's really strange is the "wat" entry
<rqou> in Y=1 it comes from an LE
<rqou> and in Y=4 it comes from some random wire?!
<rqou> waaaaait a minute
<rqou> it comes from an LE _one tile up_
<rqou> azonenberg: carry chains?
<rqou> that would also explain why the top tile has something different instead
<azonenberg> lol
<azonenberg> that would make a lot of sense
<azonenberg> but one tile UP?
<azonenberg> do carry chains run down in altera stuff?
<azonenberg> in xilinx they go up
<azonenberg> lsb at bottom
<rqou> yeah, in this chip they run down
<azonenberg> Then i'd say thats probably it unless yo found them somewhere else
<rqou> no, as in, this isn't the carry chain afaik
<rqou> this is the path that lets you make use of the last carry out
<azonenberg> oh i see
<azonenberg> So carry out to fabric, for big adders or osmething
<rqou> yeah
<azonenberg> and there's no carry-out from the LSB
<azonenberg> or wait
<azonenberg> top is msb?
<azonenberg> or what
<rqou> top is lsb
<rqou> when the carry is done, it enters the tile below
<rqou> i think
<rqou> i haven't fuzzed any logic-related control bits at all lol
<rqou> i've been attacking only the hard parts first
<azonenberg> So there's no carry going into the lsb
<azonenberg> Which makes sense
<rqou> also, this path isn't in the manual afaict
<rqou> what's interesting is that altera manuals are actually quite decent if you're just a normal user
<rqou> they're just bad for doing RE
<rqou> whereas xilinx seems to be the opposite :P
<rqou> manuals good for RE but suck for using the part :P :P
<rqou> also the top/bottom ios really do have "short" wires hacked in somewhere
<azonenberg> lol
<rqou> yup, new fuzzer is discovering routes
<rqou> so i am missing a few
<rqou> whoops, crashed sublime
<rqou> turns out sublime gets unhappy if a file changes in a directory it's monitoring every 5 seconds
<azonenberg> lol
<rqou> bonus unfun if the file is 220k lines
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<digshadow> tinyfpga: sounds like you got all the tinyfpga board clock stuff sorted out, let me know if you need any additional info / help
<whitequark> rqou: that's a bug
<whitequark> they get fixed occasionally, it used to be much more crashy
<whitequark> but also the linux inotify API is just utter shit
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<rqou> oh yeah, I've tried to use it before
<whitequark> awygle: poke?
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<awygle> whitequark: hey
<whitequark> awygle: can you finish the ice40 symbol?
<awygle> whitequark: yes. either tonight or tomorrow.
<whitequark> thanks!
<awygle> today is the last day of extreme business. i plan to devote much of the weekend to catching up on things like glasgow
<whitequark> i was sick the last few weeks but i'm picking up stuff...
<whitequark> oh cool!
<awygle> glad to hear you're feeling better :)
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<awygle> fuck APIs designed before size_t existed
<rqou> awygle: ssize_t :P
<awygle> why tf does ssize_t even
<awygle> what does it mean to have a negative size
<awygle> and why don't all these old-ass APIs at least take unsigned for fuck's sake
<awygle> no one has ever wanted to received -6 bytes from a socket
<rqou> but but how else do you create trivial RCEs? :P
<qu1j0t3> rqou: We'll find other ways. It's C, after all.
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<whitequark> awygle: ssize_t is for pointer differences i think?
<whitequark> wait no, that's ptrdiff_t
<whitequark> oh
<whitequark> ssize_t is for functions like read that return either a size or -EWHATEVER
<whitequark> and it's not in C, it's in POSIX
<whitequark> goddamn
<awygle> yup
<awygle> but it's not a size
<awygle> i guess size_or_error_code_t was too long to type
<rqou> no Option in C
<whitequark> esize_t
<awygle> soec_t
<awygle> sizeish_t
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<pie_> types i didnt even know exist
<pie_> well, not that i code much c
<awygle> i'm working with heavily OO code for the first time in ~years and i'm annoyed by how many methods are either void Func() or else take a billion parameters. struggling to find a good middle ground.
<digshadow> for ice40, is there a way to report device utilization from an asc file?
<digshadow> (ie using icestorm)
<awygle> digshadow: i think you need to use arachne for that, since it will depend on packing
<awygle> (among other things)
<digshadow> that is the place and route tool
<digshadow> I'm not using that
<digshadow> I only have the asc
<awygle> i'm aware. i don't think there's a way to do it just in icestorm. i could be wrong though.
<digshadow> got it