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<digshadow> I'm trying to use lattice icecube2 but synthesis keeps failing with this message
<digshadow> p, li { white-space: pre-wrap; } Job: "compiler" terminated with error status: 2
<digshadow> I don't see any indicator in the referenced file as to what happened
<digshadow> not seeing a lot of info online about this
<digshadow> have others experienced this?
<digshadow> p, li { white-space: pre-wrap; } See log file: "/home/mcmaster/ice/cube/test1/test1/test1_Implmnt/synlog/test1_compiler.srr"
<digshadow> this file just repeats lines like (one for each failure)
<digshadow> $ Start of Compile
<digshadow> #Mon Jun 25 18:15:15 2018
<digshadow> think it was /bin/sh vs bash
<awygle> Yeah you have to set /bin/sh to bash instead of dash on Ubuntu at least. Lattice expects Red Hat
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<rqou> whee, automated fuzzer > manual fuzzer
<rqou> since manual fuzzer missed some settings
<awygle> whee
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<rqou> hrm, something is weird
<rqou> 13 settings for an 8-bit mux?
<rqou> wait wut
<rqou> something is totally wrong with this
<rqou> the two muxes don't have the same number of bits?!
<rqou> lol false alarm
<rqou> apparently i didn't press shift hard enough and made a typo :P
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<rqou> wtf
<rqou> async clears are doing something weird
<rqou> i can only seem to route one global in
<rqou> oh wait
<rqou> this is in the datasheet
<rqou> "The LAB column clocks [3..0] are
<rqou> multiplexed down to two LAB clock signals and one LAB clear signal."
<rqou> so that's actually expected behavior lol
<rqou> azonenberg: ping?
<azonenberg> rqou: ack
<rqou> how's your house going?
<azonenberg> We passed plumbing, hvac and caulk/seal inspections today
<azonenberg> unexpectedly, the guy signed off on framing too
<rqou> nice
<rqou> wait, unexpectedly?
<azonenberg> we wanted to wait until we had the last little bits of 2x4 to hold up sheetrock in place
<azonenberg> so we didnt request the framing inspection today
<azonenberg> but everything remotely structural was done, so he said it was good enough
<azonenberg> and signed off anyway
<azonenberg> Started hanging insulation, got 3 bales up already
<azonenberg> This inspector was pretty chill, as with the other one
<rqou> "house won't instantly fall down; builder at least skimmed the code; pass!" :P
<azonenberg> he pointed out one minor correction (we need to caulk where wires enter electrical boxes on exterior walls, to prevent drafts) but as with the electrical inspection
<azonenberg> it was a de minimis violation and one that could be easily corrected without a return visit
<azonenberg> i missed that one b/c it's in the *building* code, not the *electrical* code
<azonenberg> So the electrical inspector didnt care
<azonenberg> the city building inspector did :p
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<rqou> so can you finally put in sheetrock now? or still something else that needs to be done?
<azonenberg> So far i've only hung insulation in the walls, and in areas where i didn't have to avoid any major obstacles (electrical boxes, pipes, etc) or cut half-width batts to go in non-integer-sized stud cavities
<azonenberg> We cant sheetrock yet, no
<rqou> wtf
<rqou> how many steps of inspection are required to retrofit a house?
<azonenberg> What remains to be done is... fix one minor electrical violation, caulk the electrical boxes
<azonenberg> install a few more studs downstairs so sheetrock has something to attach to
<azonenberg> Install all of the insulation currently filling the living room
<azonenberg> And that's just for the exterior walls
<rqou> O_o that's a lot more insulation than when i was over there :P
<azonenberg> Lol
<azonenberg> We got five pallets of it delivered
<azonenberg> This is for the exterior walls (R-15 faced)
<rqou> which, btw, was a _month_ ago
<rqou> so you're like 2+ weeks behind what you estimated
<azonenberg> For the ceiling, we have R-38 faced going up
<azonenberg> then R-21 unfaced on top in a second layer, to provide additional insulation where it fits (we can't fit the second layer within a few feeet of the edge of the roof, not enough height available)
<azonenberg> Then we have some R-15 unfaced going up in interior walls
<azonenberg> mostly around our bedroom for soundproofing, and around the bathrooms to hold heat in the shower area
<azonenberg> but we will likely have some left over (there's a large MOQ for ordering direct from the manufacturer) so we can probably soundproof some other bedroom walls too
<azonenberg> And this isn't even all of it
<azonenberg> We have two more pallets out in the driveway that we haven't brought in the house yet
<azonenberg> (these photos, collectively, show ~3 pallets worth)
<rqou> hmm is it just me or does the house look overall a lot nicer? did you sweep/vacuum again?
<rqou> i seem to see a lot less random demolition debris
<azonenberg> We did multiple passes of cleanup
<azonenberg> vacuuming, sweeping, general picking up junk
<azonenberg> moving tools out of the way
<azonenberg> now that rough electrical is done all of the spools of wire and conduit are out of the way
<azonenberg> We still have a thousand feet of MC in the garage waiting for us to re-hang the cable trays
<azonenberg> (that's my estimate of how much will actually be in the trays for the home runs)
<rqou> i'm specifically noticing that there seems to be a huge reduction in random sheetrock fragments in corners
<azonenberg> oh, yeah we definitely cleaned that up a lot
<azonenberg> i mean we're getting closer to moving in
<azonenberg> i'm taking off work this week and plan to spend all week hanging insulation and doing other misc stuff
<azonenberg> May not finish insulation this week but should at least get all the walls done
<azonenberg> the ceilings might have to wait
<rqou> how many more inspection steps?
<azonenberg> Insulation, then sheetrock, then final electrical, then building-wide final
<rqou> wtf insulation also has its own inspection?
<azonenberg> Yeah
<rqou> why?
<rqou> it's your energy bill
<azonenberg> Until you sell the house
<azonenberg> then it's the next poor sucker
<awygle> yeah but global warming. also usually the builder isn't living there.
<azonenberg> Plus, your neighborhood has a vested interest in clean air
<azonenberg> Which means you using less power
<azonenberg> etc
<azonenberg> Honestly, i plan to do my own insulation inspection
<rqou> wait you can do that?
<azonenberg> i mean before the official one
<azonenberg> as soon as everything is hung i'm gonna do a walk-through with the FLIR looking for leaks
<azonenberg> I'm doing my own QA on as much stuff as i can and, in most cases, testing to higher standards than the official inspector because i can afford the time
<azonenberg> 1kV hipot testing on every cable run
<rqou> > can afford the time
<rqou> > original lease was ending a month ago
<azonenberg> Thermography of every wall after insulation
<azonenberg> Thermography of every electrical box, under load
<azonenberg> Lol yes but we extended
<azonenberg> we have a month plus a few days
<awygle> can't afford help, can afford fancy thermal camera :-P
<rqou> ^ that too
<azonenberg> to hang insulation and sheetrock plus finish work
<azonenberg> awygle: i got it for SAR, not for building inspection
<awygle> (unlike rqou I'm just trolling)
<azonenberg> :p
<azonenberg> i actually took it on a search last weekend, handheld still b/c the head brackets are taking their sweet time to come
<azonenberg> in daylight so less effective than at night
<rqou> are the brackets itar? :P
<azonenberg> rqou: i believe so
<rqou> W H A T
<azonenberg> export controlled for sure
<azonenberg> possibly itar
<rqou> for a shaped piece of plastic?
<azonenberg> plastic? lol
<azonenberg> these are all cnc'd steel or aluminum
<rqou> fine, a shaped piece of metal
<azonenberg> with matte black paint, probably specially tuned for low reflectivity in IR too
<rqou> although i guess ultracentrifuges are also just shaped pieces of metal
<azonenberg> But more importantly, it's designed specifically for night vision equipment
<azonenberg> in the same way, a random buck converter PCB is going to be ITAR if it's designed specifically for a missile guidance project or something
<azonenberg> (vs the same board would not be if it was a COTS module they just threw in)
<rqou> so azonenberg, fun max v feature
<rqou> there are four global wires, but only three can enter a tile
<rqou> but the bitstream seems to have room for all four
<rqou> but the datasheet explicitly says only three
<rqou> but there are two async clear wires in the tile
<rqou> wtf are they optimizing?
<rqou> also, afaict, the one global wire input can drive onto either async clear wire
<rqou> so they cheaped out on one mux?
<rqou> why would they do that?
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<azonenberg> avoiding another metal layer on the ide? idk
<rqou> arrgh i just can't figure out wtf is going on with these clear signals
<rqou> it doesn't help how you can't select _which_ clear signal you end up using
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<rqou> wow these bits are just thrown in the bitstream every which way
<azonenberg> lol
<azonenberg> if it doesnt make sense, there's probably physical layout involved
<rqou> well, these are also just a giant pile of "misc"
<rqou> azonenberg: ok, does this make sense?
<rqou> 4 bits each for each async reset signal
<rqou> one bit = used/not used
<rqou> another for global mux vs local mux
<rqou> another for mux 4 or mux 5
<rqou> another for invert
<rqou> and finally one bit per LE to control which of the two signals gets used
<azonenberg> Seems plausible
<rqou> however, clocks seem to only have three bits each
<rqou> one for invert, one for global/local, and one for which mux
<rqou> i guess not using the clock doesn't really make sense does it :P
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<rqou> azonenberg: what do you think this means? "By default, the Quartus II software uses a NOT gate push-back technique to
<rqou> asynchronous load signal with asynchronous load data input tied high."
<rqou> to power-up high using the Quartus II software, the preset is then achieved using the
<rqou> achieve preset. If you disable the NOT gate push-back option or assign a given register
<rqou> azonenberg: i'm interpreting this to mean "this signal is an async load. we can hax it into an async set, but that eats up an input"
<azonenberg> Yep
<azonenberg> That sounds right
<rqou> why would i ever want it to do something like that though?
<rqou> that eats up one of the "useful" inputs
<azonenberg> remember what i was saying before
<azonenberg> about registers initializing to 0 in altera uarches
<azonenberg> presumably the reset signal is hard wired to one polarity
<rqou> oh, reset is a separate signal
<rqou> that always resets to 0
<azonenberg> (thats a guess)
<azonenberg> But it resets the dff
<azonenberg> if there's an inverter it sets to the opposite polarity
<azonenberg> So if you want it to not invert, you have to async-load
<azonenberg> Which eats an input
<rqou> but i basically never want to do that
<rqou> why does this chip have so many ways to footgun yourself?
<azonenberg> well with xilinx parts, in general you have a full separate init value and set/reset signal
<azonenberg> with a separate config bit for s/r polarity and init
<rqou> altera has none of those
<azonenberg> in some arches, like coolrunner, you even have separate set and reset so you can do a s-r flipflop
<azonenberg> exactly my point
<azonenberg> i think these footguns are an inherent side effect of the architecture
<rqou> instead it has separate async set, async load, sync set, and sync clear
<azonenberg> but you're more familiar with low level altera arch than me at this point
<azonenberg> I'm a 100% xilinx guy right now except for silego stuff
<rqou> er, sorry, sync load
<rqou> but yeah, it has synchronous _and_ asynchronous overrides
<rqou> and yes, the priority is defined :P
<rqou> azonenberg: also, is this chip just particularly easy or is bitstream RE just not that difficult?
<rqou> only ~1 month for ~75% completed RE (probably enough to make a blinky work)
<azonenberg> bitstream re is straightforward, just tedious
<azonenberg> especially for large chips that have more complex routing, hard IP, etc
<azonenberg> i dare you to do a GTP :D
<rqou> but somehow everyone seems to think it's "ZOMG impossibru"
<azonenberg> the number of people who even attempt it is so small
<azonenberg> that there isnt a good sample size to work with
<daveshah> I don't think IP is actually that hard, at least looking at how I would do it on the ecp5
<azonenberg> but i dont know any serious reverse engineer who's attempted a bitstream RE project and didn't meet with significant success
<azonenberg> daveshah: not hard, so much as lots of bits
<daveshah> Fixed interconnects to the fabric I have a fuzzer for already
<azonenberg> the worst part with the GTP, honestly
<azonenberg> is likely to be all of the undocumented settings you have to extract from the wizard
<daveshah> Then just go through every config bit and add it to a fuzzer
<azonenberg> i.e. you know the bits but you have to know what to set them to :p
<daveshah> Ah, maybe the gtp is a lot worse
<daveshah> Yeah
<azonenberg> in my antikernel-ipcores repo
<azonenberg> i have a config for the 7 series gtp for 1000base-x
<azonenberg> but there is basically a big table of magic numbers
<azonenberg> i have no idea what they do, the wizard gave them to me
<azonenberg> i just wrote down the numbers
<azonenberg> so i have to repeat that for every other set of settings
<azonenberg> for things like CDR PLL config etc
<azonenberg> for other bits like 8b10b coder enable/disable etc its obvious what they do
<rqou> azonenberg: do you know anything about some rumor that i vaguely recall sb0 mentioning about how some xilinx chips have a microblaze hidden _inside the transceiver_ to handle various stuff?
<azonenberg> and often (somewhat) documented
<daveshah> It's the same with the ecp5 DSPs actually
<azonenberg> rqou: i dont, but it doesnt surprise me
<azonenberg> i know altera has a hard nios in the ram controller
<rqou> wat
<rqou> how do you know this?
<azonenberg> matthiasm told me
<rqou> and why does it need this?!
<azonenberg> idk if this is documented anywhere
<azonenberg> because people dont seem to like doing ram init in rtl
<azonenberg> idk why
<azonenberg> personally, every time i did a ram controller
<azonenberg> by the time POR was done you had a bus you could feed data to and all of the training etc was done
<rqou> i thought xilinx explicitly abandoned this type of approach due to too many errata (in s6?)
<rqou> and shifted to "you just get the phasor primitives and everything else is soft"
<daveshah> It's in the datasheet even
<rqou> goddammit
<daveshah> Gah irc cloud pastes
<azonenberg> rqou: i meant every time i made one myself
<azonenberg> i didnt require any software init sequence
<azonenberg> the soft controller did the work for oyu
<rqou> that's one approach
<rqou> i'd probably go with the sb0 approach of having "the soft-core inside the fpga" manually poke the init cycles
<azonenberg> See, that's the de facto industry standard
<azonenberg> But now you have software poking random registers all the time
<azonenberg> i like encapsulated hardware
<azonenberg> where you can abstract away all of the stuff like that and just say "ok here's a ram controller, go write this data to this address"
<azonenberg> and not care what happens to do that
<azonenberg> having to poke all kidns of registers at init makes your firmware less portable and more spaghettified
<rqou> but but azonenberg, you mean you don't like having to run a special multi-kb ram init blob out of cache-as-ram mode? :P
<rqou> with so much sekrit sauce (aka SKU segmentation) that even google can't get the source code, only a special blob just for them
<azonenberg> see, in all of the socs i've built that have both a cpu and external ram
<azonenberg> by the time the cpu comes out of power-on reset
<azonenberg> the external ram is usable with no special fluff
<rqou> but but but azonenberg, how else will you manage SKU segmentation? :P
<rqou> or twiddling timings until you just avoid (or fail to avoid) rowhammer?
<azonenberg> rqou: well, to start
<azonenberg> most of my hardware is not designed to run random untrusted binary blobs fro mthe internet :p
<azonenberg> At which point rowhammer is much less of a risk
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* qu1j0t3 reads rqou in Little Red Riding Hood's voice. But Grandma, what sharp teeth you have!
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<daveshah> resisting the temptation to buy one knowing I don't have time to RE the connections to the Arria 10
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<awygle> I really wish people could and would reveal the (quantity, price) tuple they actually get from distributors for FPGAs
<awygle> I assume there's an NDA involved but the hinting is maddening
<daveshah> One data point: pricing in the UK for 100-1000 from Arrow for Zynqs was slightly more expensive than single qtys from Digikey IIRC
<daveshah> *Avnet
<pie_> i.e. 1000 for the cost of 1? or 1000 > 1000*cost of 1
<daveshah> The latter
<daveshah> But this was in the UK
<pie_> the former would have been funny
<pie_> lso insane
<pie_> so i figured
<awygle> They're both insane in different directions
<awygle> What is this meme about tar being so hard to use? There are like four useful options, all of which make total sense. Also, find exists.
* awygle woke up salty today
<qu1j0t3> i havent' seen that one, but looks like one that you can just ignore
<awygle> Fine, be all mature :-P
<qu1j0t3> :)
<kc8apf> daveshah: that monitor is still cheaper than minimum qty of the included Arria 10 GX ($2000 vs $2600)
<daveshah> kc8apf: yeah even considering volume discount it's a crazy FPGA
<daveshah> I suppose they needed the transceiver speed, if nothing else
<daveshah> seems like a lot of LCs for what can't be that complicated a task
<kc8apf> a monitor is not usually where i'd look for a "low-cost" dev board but there we have it
<daveshah> it may be that the ASIC is delayed and the PR cost of not shipping a product is greater than the margins being wiped out by the fpga
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<awygle> which arria is that?
<awygle> wow. that thing has 24 17+Gbps transceivers. that seems like overkill.
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<pie_> awygle, ill just refer to stuff like openscad as SCAD from here on out
<pie_> awygle, weird idea: scad with FFI
<awygle> pie_: expand?
<pie_> idk, once i had the thought, though i didnt really think about it much, but the first thing that seems to make sense would be to be able to call out to tools that return info in some acceptable format
<pie_> like...vertex arrays, or heck knows
<pie_> alternatively, something something build scripts and includes? :p
<pie_> just a random idea.
<pie_> ugh, rqou, im talking with someone about philosophy and i cant find an orihime "i reject" clip
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<Ultrasauce> bleach and philosophy of mind don't really belong in the same context if you ask me
<Ultrasauce> though its 'internal world' concept is kind of neat i guess
<Bike> bleach takes a nihilistic epistemological stance
<pie_> well, i didnt mean to put bleach on a pedestal, i just really wanted the I REJECT
<pie_> :p
<pie_> Bike, ooh that track seems pretty good, will listen in a sec
<Bike> yeah i like it. it's the only think i like about bleach (because i haven't seen it)
<pie_> eh, read the manga if anything
<pie_> its not super horrible (i guess), but its not great either
<Bike> that's exactly the kind of attitude that led to me not having seen bleach
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<pie_> :D
<pie_> i dont really like how most of the shinigami are jerks and yet theres a whole society somehow built on them
<pie_> alternatively, something something feudalism i guess?
<pie_> idk, i guess i dont like how the characters are done
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<awygle> Bleach's plot and characters both suck but the plot problems are masked by being utterly typical of the genre
<pie_> right
<pie_> lol
<awygle> rqou: the barrier to bitstream "documentation" is probably more legal than technical.
<pie_> lately im starting to feel like i could come up with better plots than most fan translated japanese media and i cant write for shit :(
<awygle> by which I mean primarily the uncertainty of it
<pie_> *with some effort
* pie_ mumbles something about go read a book :(
<Bike> go write a book
<awygle> Sturgeons law
<pie_> Bike, im also learning to draw. eta couple lifetimes
<pie_> :P
<awygle> I've been feeling like I want to write fiction lately, but I don't have time
<awygle> I've been scratching the itch by playing tabletop rpgs
<pie_> if i was going to describe my writing so far it would probably be a something like some egan/stephenson/gibson, and a bit melodramatic...probably really cheesy too
<pie_> ah well
* pie_ goes back to electrodynamics
<pie_> "a dramatic form that does not observe the laws of cause and effect and that exaggerates emotion and emphasizes plot or action at the expense of characterization." OH WAIT NO
<pie_> s/electrodramatics//
* pie_ also mumbles something about practicing more
<pie_> hm. sturgeons law reapplied? if you right enough, 10% might come out good? :P
<pie_> ... *write
<pie_> just sell irc logs as a book
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<pie_> Bike, guess im just salty that if it was gonna be so popular the execution could be a bit better :P , alternatively: THIS is what people want
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