<pie_> wow the pad just totally failed on the asymptotic pressure discussion x)
<pie_> s/pad/control/
<pie_> theyve been awake for a long time though, but still, point totally missed. the guys at the pad station were on about how to them it looks like the pressure slope is decreasing fast enough that theyll only reach 58 bar, guy at control was like "yeah but the slope is still positive so itll be fine"
<pie_> thats not how asymptotes work xD
<rqou> azonenberg: you're going to be at defcon right?
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<mithro> Has anyone looked at this before -> https://github.com/fangism/hackt ?
<awygle> hm. no, but apparently i clipped it to my EDA notes several months back.
<awygle> used at achronix? that's interesting. i wonder what they need with asynchronous circuits.
<sorear> whatever it is, it's major enough they named the company after it
<sorear> http://vlsi.cornell.edu/~fang/hackt/hac/Purpose.html#Purpose this is not a very complete manual :/
<awygle> achronix makes eFPGAs
<jn__> pie_: launch in 12 minutes
<pie_> jn__, yu
<pie_> p
<awygle> any idea if there's a planned hold in their sequence?
* awygle has to drive home...
<pie_> jn__, hackers are the perfect audience, never sleep
<pie_> awygle, i think theres a hold at 1 minute but i doubt theyre going to hold for long
<pie_> well, a hold or sometihng
<pie_> probably final "ok everybody confirm this"
<pie_> which is right now.
<pie_> says "final fts operations"
<awygle> flight termination system
<pie_> aha
<pie_> is that as in "abort" or..?
<awygle> that's as in "rocket headed for Philadelphia, please blow it up now"
<pie_> aha
<awygle> you send a (very strong) radio signal that causes the rocket to explode
<awygle> this is why our 450 MHz radio made range safety so twitchy
<awygle> iiuc the FTS frequency is in the 400 MHz range someplace
<pie_> dude in chat: "<Ben Brockert​>I'm a bit amazed that a student hybrid has a radio flight termination system. None of the rockets at Armadillo or Masten had, it's more typical of orbital rockets."
<awygle> that's... surprising to me
<awygle> the absence at armadillo and masten i mean
<awygle> but i wouldn't be surprised to learn europe had stricter rules
<pie_> *shrug* its a dude on the internet tho so ymmv
<awygle> wow, they're more than 6 hours outside of their planned launch window
<awygle> nice to be suborbital :p
<awygle> lol @ chat "just turn engines on"
<pie_> yep
<pie_> xD
<pie_> long day for them
<awygle> here we go
<pie_> people on about iridium having a 1 second window
<pie_> why does geosync (?) even have a window
<awygle> iridium isn't geosync
<awygle> lol nobody ever builds their cameras/links to deal with launch forces
<pie_> video lagged the fuck out
<awygle> ooof did that just explode? that's sucks.
<pie_> ugh
<pie_> im not sure if it actually exploded or just...fell apart
<pie_> so what....300 meters?
<pie_> :/
<pie_> oh oops i paused the stream
<awygle> that's heartbreaking
<pie_> :C
<pie_> man really sucks for such a long day
<pie_> well...at least they get to experience post-failure research now :'(
<pie_> "<Si_Phi​Good> luck with your data review 😕"
<pie_> oh shit, that does look like some sort of explosion but it looked pretty weird
<pie_> and a second later it disintegrates?
<pie_> so many trolls in chat
<pie_> awygle, well, guess you can drive home now :(
<pie_> its a little frustrating that the video freezes immediately on ignition
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<pie_> lol "<The TruManZoo​it> might have crashed into the dome hahah"
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<pie_> so frame by frame, assuming the black and white is a heat camera? theres an explosion at about -0:17, whatever the ring is, after a few frames it expands
<pie_> i dont suppose thats just shockwaves from passing the sound barrier?
<pie_> well...thats all the armchair rocketry from me for today
<pie_> well, one of those things has to be the tank exploding since 2-3 seconds into burn it should still be under a lot of pressure
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<awygle> https://github.com/termoshtt/accel this is cool as _hell_
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<prpplague> tinyfpga: hey, are the kicad files up github out of date for tinyfpga-bx ?
<tinyfpga> Hmm...I think they are up to date, but I will
<tinyfpga> ...have to look at it tomorrow morning
<prpplague> tinyfpga: no worries, but the card i have that came with my BX shows VIN, GND, 3.3V
<prpplague> tinyfpga: the kicad design files, have VIN, 3.3V, 1.2V
<prpplague> tinyfpga: for the power pins
<tinyfpga> prpplague: I think your looking at the wrong repo...bx is here: https://github.com/tinyfpga/TinyFPGA-BX
<tinyfpga> The bx ended up being significantly different than the b2, so I gave it a separate repo
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<prpplague> tinyfpga: oh lovely
<prpplague> tinyfpga: that wasn't clear at all from the website, hackaday.io or any of the other material i had seen
<prpplague> tinyfpga: well it's fixable with an exacto knife on this revision...
<prpplague> tinyfpga: really should add something to the "b-series" readme
<prpplague> tinyfpga: "if you are looking for bx go here"
<tinyfpga> prpplague: good call, I’ll update the readme for the B2 repo and hackaday and point people in the right direction
<prpplague> tinyfpga: thanks
<tinyfpga> prpplague: I’m so close to it that I take these things for granted...
<prpplague> tinyfpga: understood, that is why i take the time to comment on such
<tinyfpga> prpplague: what are you making?
<prpplague> tinyfpga: i was on a tight schedule and having a dxf and pinout before i received the boards was a major issue
<prpplague> tinyfpga: proof of concept for a customer product
<prpplague> tinyfpga: they have a VC demo in a week
<prpplague> tinyfpga: i do a lot of proof of concept and demo items on quick turn
<tinyfpga> prpplague: so...the guide does reference the BX repo on a couple places, but I can definitely understand how that could be missed
<tinyfpga> prpplague: I think I’ll add a message to the top of the B2 README so it’s very clear to anyone that goes there but is looking for the BX
<tinyfpga> prpplague: let me know if there’s anything else I can do
<tinyfpga> The big incompatibility between the pinout is the power/gnd connections
<prpplague> tinyfpga: yea i went back and read through and there are places
<prpplague> tinyfpga: but when i read "b-series"
<prpplague> i just assumed Bx was part of B-series
<tinyfpga> prpplague: yup, that’s where it’s confusing
<prpplague> tinyfpga: i got it fixed on these boards with a little rework
<prpplague> tinyfpga: so no biggy for me
<prpplague> tinyfpga: but it's a great product, i'd hate for it to get a bad name because of such confusion
<tinyfpga> prpplague: thanks!
<tinyfpga> prpplague: hope your project goes well!
<tinyfpga> prpplague: let us know if it ever makes it out into the market
<prpplague> tinyfpga: yep will do, for real product, we'd probably switch to the UP5K
<prpplague> tinyfpga: but so far, i know i'll keep the Bx in my "tool box"
<prpplague> tinyfpga: made some altium footprints for it
<prpplague> tinyfpga: so i can throw it into quick turn designs
<tinyfpga> prpplague: awesome
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<whitequark> daveshah: nope
<whitequark> it's an uh
<whitequark> it's a SMIA (MIPI CSI-2) camera I desoldered from some Nokia phone mainboard I pulled out of a junk pile.
<daveshah> Interesting
<whitequark> mfgr 0x09 model 0x3b2f, if you're wondering
<whitequark> SMIA is actually very sane
<daveshah> I'm working on a MIPI CSI-2 core for the iCE40 atm (I wrote one for the Xilinx 7-series in VHDL a while back)
<whitequark> it's a plug-and-play spec written by people who actually give a fuck about being able to use their hardware, as opposed to e.g. UVC
<whitequark> ah huh
<daveshah> Sounds nice
<whitequark> mine will be in Migen
<daveshah> sounds nicer than normal CSI-2 tbh
<whitequark> hm
<whitequark> really?
<whitequark> it's still using MIPI CCI
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<daveshah> The CSI-2 is alright
<daveshah> It's the near-undocumented I2C configuration register map that every CSI-2 camera I know has that's the pain
<daveshah> Is that the same with SMIA?
<whitequark> I dunno, I read the SMIA spec in half a day, wrote register definitions in the next half day, and now I have the camera outputting a test pattern alright
<whitequark> hm
<daveshah> So SMIA standardises register definitions?
<whitequark> apparently
<whitequark> I thought this is a part of MIPI, actually
<whitequark> but guess not
<daveshah> No, CSI-2 cameras all have their own I2C register maps
<whitequark> the register definitions and values are *extremely* good in SMIA
<whitequark> you have directly encoded clock divisors/multipliers for example
<daveshah> The only way you can get something working is copying the exact init sequence from a Linux kernel driver for the camera
<whitequark> none of the mess with "divide by two and subtract 1 and don't use these patterns"
<daveshah> Yeah, that's much nicer
<whitequark> the camera explicitly tells you every single limit it has
<whitequark> clocks, frame size, scaling, whatever
<whitequark> actually the SMIA registers contain -everything- you need to get the camera running
<daveshah> that's really nice
<whitequark> it might not run in the absolute best way it can, but it does already run, and I spent exactly 2 days on this
<whitequark> from not knowing what SMIA is and only having a camera on the socket in the junk phone to having an LVDS bit stream
* daveshah spent three weeks getting an Omnivision camera working as I wanted :(
<whitequark> amazing
<whitequark> so I lucked out
<daveshah> Seems like you definitely made the right choice of interface
<whitequark> now I'm slightly stuck because the lowest this camera goes is 40.5 MHz
<whitequark> and... the UP5K struggles to clear 33 MHz with just my I2C core
<daveshah> is that DDR?
<whitequark> oh right, DDR exists
<whitequark> thank
<daveshah> you might have to run the "SERDES" part at a higher clock rate than everything else
<whitequark> yes but icetime is not able to do anything meaningful with such designs
<whitequark> which is annoying
<daveshah> tbh as I'm doing CSI-2 stuff too let me see what I can do with icetime
<daveshah> Just as far as treating the clock domains as separate, don't plan to do cross-clock stuff yet
<keesj> any apio people here?
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<kc8apf> keesj: users maybe; devs, not so much
<cr1901_modern> I mean I use atom, but I don't use apio... I just put everything in a Makefile or whatever
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<awygle> apio looks really cool
<awygle> and i know tinyfpga supports it for his boards
<keesj> it looks ok (the atom + apio thing) and it was quite easy to adapt the UART demo to run like that. it looks like a nice (but simple) effort in having a more integrated environment.
<keesj> but it also has it's own iverilog and toolchain so .. might also start working against me
<keesj> (the uart demo was for the icestick board) I have yet to blink tinyFPGA
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<awygle> apio-ide for me was one of those "oh this doesn't exist, i should make it, but i'm busy" *three months later* "oh hey somebody made it!" things
<daveshah> My only niggle is that their builds aren't so frequent
<daveshah> It took about four months for up5k support to arrive in it iirc
<awygle> that's life on the bleeding edge
<awygle> gotta build everything from source
<keesj> tinyfpga: talked about it in the amphour podcast (I don't remember the details) but he talked about an altnernatives (https://theamphour.com/395-an-interview-with-luke-valenty/ )
<mithro> daveshah: 4 months seems pretty fast to me :-P
<keesj> hmm the show notes also say https://github.com/SymbiFlow Symbiflow is the next gen of opensource tools
<daveshah> mithro: certainly compared to distro packaging
<mithro> keesj: I'm sure that apio will eventually package symbiflow stuff when it is ready for people to actually use.
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<zkms> nice; the "side channels from digital sections of mixed-signal ICs get upconverted into RF by the mixers" paper got published http://www.s3.eurecom.fr/docs/ccs18_camurati_preprint.pdf
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<awygle> but i've never heard of tricholoroethane as an etchant. wonder if it'd take CuCl or FeCl
<sorear> How sure are we this only affects mixed signal chips and not multi-chip systems with ordinary electrical coupling?
<awygle> considering how easy it is to make a 4-fet mixer, i wouldn't be at all surprised if it happened all over the place
<awygle> actually you don't even need that much, can do it with a diode
<daveshah> Hehe other direction but I could receive AM well just by connecting a LO square wave and a long wire antenna to the same opamp input
<bubble_buster> hmm. TIL of Language Server Protocol, seems there isn't one for verilog, might be a cool project
<bubble_buster> anybody here looked at that?
<awygle> i'm aware of it through Rust, mostly
<awygle> i am generally in favor
<awygle> i'm generally in favor of anything that turns an mxn problem into an mx1 problem and a 1xn problem
<awygle> lots of people complain about it being out-of-process RPC based and that's not unreasonable but i'd rather have something potentially inefficient than have nothing
<bubble_buster> yeah. I think my top two projects if I didn't have to do research/thesis would be this LSP/Verilog thing and
<bubble_buster> integrating this HLS tool with yosys/riscv/axi or wishbone instead of quartus/NIOS/avalon
<bubble_buster> called LegUp. I'm working with it for my thesis
<awygle> huh, there's one for VHDL
<bubble_buster> yeah
<awygle> "Do you plan to support Verilog?" "One day."
<awygle> how much of a parser do you need to do LSP?
<bubble_buster> no idea
<awygle> my pet "should be somebody else's project" is a good systemverilog parser, as a first step to support in oss tools
<bubble_buster> to get all the features I would guess you would need a complete parser
<sorear> Out of process isn’t my favorite thing ever but given the sorry state of dynamic linking it’s reasonable
<bubble_buster> I'm not sure how LSP is set up but I assume you need not only a complete parse of a file to begin with, but also a way to do a quick O(1) update when edits are made
<awygle> sorear: yeah, dynamic linking and FFI both suck so bad that RPC is probably the best most flexible option.
<sorear> counter-counter-point: if you have plugins in an unsafe or single-threaded language, serious editors will try to isolate them in a process or process equivalent anyway
<awygle> also true. so why not just let the OS do it
<awygle> actually i have complaints about _IPC_ in this context too. but never mind.
<sorear> even something like Java you increasingly have to isolate because of how much Thread.terminate has been weakened
<awygle> hm, surprised i can't find any evidence of UV laser engravers used for PCB lithography (or really of UV laser engravers at all that aren't a billion dollars)
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<awygle> oo cool, thanks!
<kc8apf> awygle: minimal LSP is regexs
<kc8apf> basically just fancy syntax highlighting rules
<kc8apf> full LSP support includes deep understanding of the AST to do autocompletion, error highlighting, etc
<rqou> awygle: it exists
<awygle> that's about what i figured yeah
<rqou> no link on hand but some hobbyists have tried attaching Blu-ray burner lasers to an xy mechanism
<reportingsjr> awygle: are you saying in general, or just hobbyists?
<rqou> for exposing photoresist
<awygle> reportingsjr: i was really saying "in my price range" lol
<reportingsjr> ah, right
<awygle> i found some 20k+ industrial equipment
<reportingsjr> was gonna say.. many modern board houses actually use UV lasers to cure photoresist nowadays
<awygle> but i also found a 1W 405nm laser head for 17$
<awygle> (not UV but supposedly within the band that will work, if slower)
<rqou> yeah, those are probably for Blu-ray burners
<awygle> probably
<awygle> in addition to reportingsjr's link above i came across https://www.youtube.com/watch?v=va0taOtdYPQ as well
<rqou> that might be the one I'm thinking of
* genii slides qu1j0t3 a coffee
<awygle> oo good idea
<kc8apf> antl4's contributed grammars repo has edif 3.00, smtlibv2, verilog, and vhdl. Verilog seems to be missing a few pieces but a decent start
<qu1j0t3> genii: thanks
<sorear> "missing a few pieces" relative to all of 1800:2017, or some smaller target ?
<kc8apf> 2001
<kc8apf> they included comments that cite the specification section by section
<kc8apf> a few parts are commented out
<genii> Some guys that did the bluray PCB XY http://www.diyouware.com/DiyoPCB-MKI and then a later all-in-one "PCB mini-factory" incorporating it http://www.diyouware.com/node/202
<kc8apf> UDP declarations are commented out for instance
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<rqou> azonenberg, awygle: do you know of any existing evil-maid toolkit for macs?
<prpplague> genii: that's cute
<genii> prpplague: If you read the accompanying blog, it details how they reverse-engineered the laser tracking mechanism, etc
<prpplague> genii: got it in my cue
<prpplague> tinyfpga: hey, it would really be nice if the enable for the 3.3V LDO was connected to VIN via a 0R, as it is now, i have to remove the LDO all together
<prpplague> tinyfpga: just a comment for future revisions
<tinyfpga> prpplague: ok, I made a GitHub issue for it
<prpplague> tinyfpga: silly me, i should have just done that
<tinyfpga> prpplague: :)
<m_w> ut oh prpplague has joined the fpga party
<prpplague> m_w: well i am sure tinyfpga does think it's a party, all i've been doing is complaining, hehe
<tinyfpga> haha
<tinyfpga> It’s all good :D
<prpplague> m_w: you up on kicad5?
<m_w> prpplague, I have been using bleeding edge for a while
<m_w> need to grab the latest release actually
<m_w> think I am at 5-0.0-rc2
<prpplague> m_w: latest stable seems good, but the library stuff still sucks imho
<prpplague> m_w: i want to design stuff, not spend 90% of my time fighting with libs
<m_w> prpplague, I have been using kicad for a while now and can easily navigate the backassward library process
<prpplague> hehe
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<m_w> the netlist export part has gone away with 5
<m_w> the sync is more automatic like altium
<prpplague> yea
<prpplague> but all the projects i seem to open need a bunch of remapping done
<m_w> that is a new kicad 5 thing
* prpplague hijacks the channel to whine and complain about kicad
<m_w> there is #kicad to troll for those needs
<m_w> here is where complain about not a having VHDL front end for your tools
<prpplague> m_w: hehe
<m_w> tinyfpga, so you are thinking of going to the winter of hardware with olafk?
<prpplague> m_w: i hope you are being successful in avoid the J-parasite....
<awygle> no VHDL, no SystemVerilog, no same library management
<awygle> *sane
<m_w> :)
<tinyfpga> m_w: that’s the event in October he’s planning, right?
<awygle> only Zuul
<m_w> yeah, during gsoc
<prpplague> winter of hardware?
<m_w> I was a absentee mentor this year but am more interested hardware
<prpplague> "winter is coming!"
<m_w> *in hardware
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<awygle> i was thinking about trying to make it out there too
<m_w> last time I went to GSoC mentor summit got to hang out with the fossi guys
<awygle> kind of a weird time period, but i am gonna miss orconf so...
<prpplague> m_w: NORConf!
<m_w> warthog9 was there along with av500 and nerdboy
<m_w> good times
<prpplague> awygle: i've been debating on going to this years ORConf
<prpplague> awygle: it's a little out of the way for me
<awygle> yeah Gdansk seems hard to get to
<prpplague> hehe i meant poland in general, hehe
<m_w> gsoc is not keeping my interests anymore so I worked in some hardware components
<prpplague> m_w: hehe, you know i did GSoC for a while too, gave up on that
<prpplague> m_w: i had not heard they were letting in hardware projects
<m_w> if there was a norconf / winter of hardware I would go for that instead
<prpplague> hehe $3700 round trip to poland
<m_w> was sneak over to silly valley in october :)
<prpplague> m_w: where in sv are they holding the WiH?
<m_w> well he is at google proper
<m_w> so the bar next store :)
<m_w> next door
<m_w> jeeze I type like a 5th grader
<prpplague> m_w: you make schematic symbols like a 5th grader
* prpplague makes engineer insults
<m_w> don't make fun of the lofive
<m_w> it has feelings too
<prpplague> m_w: you schematic symbols are so fat and ugly, even the ERC won't touch them
<prpplague> m_w: hehe
<m_w> ERC is whimps
<m_w> don't need no stinking ERC
<prpplague> hehe
<m_w> and my symbols are immaculate
<prpplague> hehe
<m_w> prpplague, what are you making with tinyfpga?
<awygle> ugh. is CRC32 unambiguous?
<awygle> of course not.
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<azonenberg> awygle: i normally say "802.3 CRC32" to avoid confusion
<azonenberg> even specifying the polynomial isnt unambiguous as there's like 3 different ways of calculating a crc
<azonenberg> and you do various transformations to encode the polynomial for each :p
<awygle> oh i'm aware lol
<awygle> but like CRC16-CCITT is (mostly) unambiguous because it specifies the algorithm
<awygle> so i thought CRC-32 might be similar, but it's not
<azonenberg> yeah CRC32-Ethernet is unambiguous
<azonenberg> CRC32 is not
<awygle> semantically, do you think a CRC counts as a hash?
<azonenberg> (there's also many other CRC16s that are less common)
<azonenberg> And yes, a non-cryptographic hash but still a hash
<awygle> again - very aware :p
* awygle has CRC-related trauma
<awygle> does a checksum count as a hash? :p
<sorear> CRCs, if you pick a random irreducable polynomial, are an example of a universal hash function family
<prpplague> <m_w> prpplague, what are you making with tinyfpga?
<prpplague> m_w: sekrit Stuff