<rqou> uh, it's not linker-dependent
<rqou> there's a spec for it (for ELF)
<kc8apf> hmm
<kc8apf> I don't think there is for MachO
<kc8apf> perhaps format-dependent
<rqou> yeah
<kc8apf> MachO has a concept of two-level namespacing
<rqou> offtopic: why does everything in "enterprisey Windows" seem needlessly overcomplicated and obfuscated?
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<awygle> Because you don't know it
<awygle> At the risk of sounding like rqou, why the hell is LoRaWAN getting so much play in Maker/Osh spaces?
<kc8apf> long range, decent bandwidth, low cost
<awygle> It's like, *extremely* proprietary, isn't it?
<kc8apf> yup
<awygle> Not clear to me why it's better than eg cc1100
<kc8apf> but I can get LoRaWAN transit from Comcast now
<awygle> Really? Weird. I gotta Google that
<kc8apf> LoRa gets you really impressive range. 20-30 miles easily.
<mithro> awygle: I think someone is doing a decent job of marketing
<rqou> <troll>but morse code over shortwave gets you the entire planet</troll>
<kc8apf> data rate is terrible
<kc8apf> RTTY and AX.25 can get you at least 300 baud over HF
<zkms> oh hey have you heard of the people doing high-frequency trading over HF (like, shortwave, not microwave)
<kc8apf> because ionosphere bounce is faster than fiber and LEO?
<zkms> yep
<sorear> I'm eagerly awaiting the day neutrino communication becomes possible for those with money to burn and modest data rate reqs
<zkms> (tbf it's sorta an easier problem, they have lots of 100% reliable fibre bandwidth and GPS antennas on both sides so they can do modulation/coding-scheme negotiation, exchange channel sounding information, maintain protocol state, etc, all over the fibre link and not over the HF link)
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<rqou> sorear: can't we technically already do that by turning a nuclear reactor on and off? :P
<sorear> i suppose yes, although the data rate is *terrible*
<sorear> and the range isn't that great
<kc8apf> next year's flashing light content: blink a light at 1Hz using a nuclear power source
<sorear> there's a proposal to site the second Hyper-Kamiokande tank in South Korea instead of the current Japanese facility and I'm certain geopolitics is playing absolutely no role in the process
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<mithro> Has anyone seen / got a tool which converts between verilog specify files and sdf format?
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<rqou> azonenberg: ping?
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<awygle> I have met some traders working on free space optical links
<rqou> just to be a little bit faster than fiber?
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<awygle> Yup. Because 0.999c > 0.67c
<awygle> (approx.)
<awygle> also "blink a light at 1hz using a nuclear source" sounds pretty doable
<awygle> tbh
<rqou> so azonenberg didn't want to do open-source nuke-to-blow-people-up, but maybe we can do open-source nuke-to-make-energy? :P :P :P
<awygle> I mean the crappiest rtg could blink an led at 1hz
<awygle> (probably)
<rqou> i mean, i bet even the nurdrage nuclear battery hack can blink an led
<awygle> Tritium was my first thought
<awygle> Americium was my second
<awygle> In both cases I immediately got carried away designing direct conversion cells instead of PV or TC
* awygle loves nuclear energy
<rqou> but but but don't you know, terrorists could use them to cause massive damage!oneone :P :P :P :P :P
<rqou> amidoinitright?
<awygle> Only if they attack the weak point
<rqou> i have no idea what current anti-nuclear FUD is like
<awygle> yeah idk either
<rqou> a bunch of people on birbsite were talking about it, so some group must have said something
<awygle> Greenpeace EU yeah
<awygle> Something about flying a plane into a reactor being way easy to do
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<azonenberg> greenpeace: environmentalism's worst enemy since $YEAR
* azonenberg wonders how many tons of CO2 emissions could have been avoided if they hadn't been campaigning so hard against nuke plants
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<rqou> azonenberg: so, can i get a mini-design review?
<rqou> how's this for babby's first bga fanout?
<awygle> looks design rule driven. are those all the signals you need?
<rqou> yes
<rqou> also, i'm being a bit conservative and designing for 6/6 even though the oshpark process is 5/5
<rqou> and vias are definitely larger than minimal, but when i did do min-sized vias they always looked a bit sketchy on oshpark's process
<awygle> it doesn't look terrible offhand, couple things I'd do differently but just stylistic
<awygle> you're not going to take my advice and use seeed or dirty or jlc?
<rqou> probably not
<rqou> honestly i trust those fabs even less
<awygle> fair enough
<awygle> I've never actually had a problem
<awygle> but I understand the concern
<awygle> the cost difference is like 5x though hence the recommendation
<awygle> (not even counting the greater quantities)
<rqou> hmm i'll check
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<rqou> given that this isn't _that_ demanding a board
<awygle> shouldn't be no
<rqou> i think i'll probably stick with conservative design rules iether way
<awygle> sure, good not to push the envelope if you don't need to
<awygle> i'ma sleep now, have fun routing
<rqou> from my surveying oshpark seems to have the smallest min hole size of all these cheap fabs
<awygle> that's very true
<rqou> but it seems oshpark is pushing the fab a bit with those dimensions
<rqou> i've noticed via drills looking like they're just barely not breaking out
<azonenberg> rqou: i normally use 550/300 um trace/space as my standard via
<azonenberg> sorry i meant
<azonenberg> 550/300 pad/drill
<rqou> wtf i don't know um
<azonenberg> then drop to 500/300 or 460/300 if i really need it in a tight spot (thats their design rule limit)
<rqou> i'm using 12 mil drill 24 mil pad
<azonenberg> they do 10 mil drils
<rqou> i know
<rqou> it always looks sketch af
<azonenberg> I use oversized pads to reduce the risk of breakout
<azonenberg> 457 um is their design rule limit
<azonenberg> i use 500 in tight spaces and 550 everywhere else
<rqou> or maybe that's because minimum annular ring is a bit too small
<azonenberg> yes, the annular ring spec is really tight
<azonenberg> the drills are fine
<rqou> also, many other fabs don't do down to 10 mil
<azonenberg> but i think they're exaggerating the annular ring capability
<azonenberg> its way smaller than any other cheap fab
<rqou> that's what i've noticed
<azonenberg> so i only use their full-spec annular rings when i have no choice in really tight spots
<rqou> i mean, most of my boards work but always make me nervous
<azonenberg> and i do it in a handful of spots on the pcb where it wouldnt be the end of the world if one failed and i had to rework
<rqou> i don't get why they advertise such tight annular rights
<rqou> *rings
<rqou> hobbyists don't need it, and people like you who do will know they're cheating
<azonenberg> its possible the fab is exaggerating their specs to oshpark? :p
<azonenberg> idk
<rqou> huh
<rqou> i thought laen would be much more strict than that
<azonenberg> i meant, the fab is lying
<azonenberg> not laen
<azonenberg> I have had no problems pushing limits on trace/space though
<rqou> i thought laen likes to torture-test fabs
<azonenberg> He does
<azonenberg> but defects still slip through
<azonenberg> i've had one board with totally borked soldermask due to a gerber merging bug
<azonenberg> i've had one with 450um drills where i called for 300 because the fab screwed up and loaded the turret wrong in the drill machine
<azonenberg> i had one with a very weird ENIG defect
<azonenberg> And at least one with dust specks or similar on the photomask (the one you caught)
<rqou> i know we went over this, but i'm still amazed just how many fab issues you seem to hit
<rqou> azonenberg: i'm curious what your working relationship with laen is like? does he love you or hate you that you always encounter weird problems?
<azonenberg> i make a lot of boards :p
<azonenberg> and we havent talked in a while actually
<azonenberg> since he stopped hanging out in #oshpark
<azonenberg> i've had more contact with pdp7
<rqou> i wonder what the average "complexity level" is of boards people make at oshpark
<rqou> apparently there's a nonzero amount of non-circuit boards (art, mechanical, etc)
<azonenberg> yeah
<azonenberg> i've actually considered using pcb for front panels
<azonenberg> you get nice silkscreened labels
<azonenberg> optional conductive elements for ground connections or indicator LEDs
<azonenberg> And milled cutouts
<rqou> yeah, definitely not a bad idea
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<rqou> azonenberg: TIL BGAs are actually pretty nice to route as long as you don't actually need all of the pins
<rqou> doing an escape is pretty relaxing and is a nice puzzle
<azonenberg> yeah
<azonenberg> and if you have enough layers, using all the pins isnt a big deal
<azonenberg> (you see why i prefer them to trying to fan out a QFP?)
<rqou> i have one part here that's a qfp with exposed pad and it's just frustrating AF
<rqou> the other qfps are ok because i either optimized their pinouts or they're only using like a quarter of the pins
<rqou> azonenberg: any obvious issues so far? https://pbs.twimg.com/media/DhfCV-0VMAAP6H6.png:large
<rqou> ugh wtf pin swapping always confuses the heck out of me
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<qu1j0t3> azonenberg: pcb front panels, wow. that's very clever
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<awygle> TIL in Washington there's no requirement for my landlord to tell me whether they intend to make a renewal offer on any particular time scale
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<azonenberg> awygle: lol
<azonenberg> yeah we encountered that...
<awygle> To a native Californian this is baffling
<awygle> Guess I'm spending the day looking at apartments
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<mithro> Anyone got a python sdf parser?
<mithro> Seems like there are a lot of things called sdf
<daveshah> mithro: there is a very partial one somewhere in icestorm
<mithro> daveshah: does that produce sdf?
<daveshah> mithro: it is primarily used to parse the sdfs that come from icecube to build the timing database
<mithro> Oh it does have a reader at line 208
<daveshah> I did play about the other day using it to get some cell timings for the ecp5
<daveshah> But it seems Diamond specifies some stuff slightly differently
<daveshah> ISTR it combined setup and hold together unlike icecube
<mithro> daveshah: I would really like to get yosys to take verilog specify and sdf files and convert them to attributes on objects
<daveshah> mithro: yeah
<mithro> daveshah: I would really like to get yosys to be able to do equivalence check when timing is involved in the future too :-P
<daveshah> mithro: that's a totally different problem domain to what Yosys does
<daveshah> I'm not even sure what you would check against?
<mithro> daveshah: I'm not sure I know what *I* mean - but for example a AND gate with unequal delays on inputs can dramatically affect the actual output -- were as when they have equal delay on the inputs you could specify it as an input or an output and the results would be exactly the same
<daveshah> mithro: this feels quite far from anything Yosys is, and a very niche problem
<daveshah> You would be in the realms of symbolic algebra I think, in the general case
<mithro> daveshah: I guess we see Yosys as kind of different things -- I see yosys as a tool which takes descriptions in one format and converts it to another format while providing checks that the conversion and descriptions are valid
<mithro> daveshah: Take converting adders to netlists -- there are many different ways to implement an adder with have different trade offs
<daveshah> mithro: yes, exactly
<daveshah> I understand what Yosys is
<mithro> daveshah: In theory you should be able to use logic equivalence to /prove/ that they perform the equivalent
<daveshah> mithro: yes, that's a common use case for Yosys
<daveshah> But none of this ties into talking about equivalence checks on numerical timing values, which is quite different
<mithro> daveshah: However it doesn't matter if they are logic equivalence if by using one form you can't meet your timing or logic usage requirements
<daveshah> mithro: Remember that Yosys has no timing support for the fpga synthesis case, and very limited support in the ASIC case using ABC
<daveshah> After all interconnect delays often dominate logic delays, so are unknowns at synthesis
<daveshah> Ultimately, you use equivalence checks and formal verification to make sure it functions, and STA to make sure it meets timing
<daveshah> I don't think anyone is interested in trying to combine the too, except for limited verification of clock domain crossings
<mithro> daveshah: At the moment we generally force humans to make the decision, it would be nice if there was a much easier way for the systems to make the decision
<daveshah> mithro: it's not exactly a difficult problem, it is a single logical and
<daveshah> design OK = formal verification passes and STA passes
<mithro> daveshah: Maybe Yosys will end up being the wrong place to add this, but eventually it will probably be wanted somewhere
<daveshah> mithro: what do you actually want to add? What inputs and outputs do you expect
<mithro> daveshah: The AND case was a trivial example, like printing the numbers 1 to 10 to show how a for loop might work
<daveshah> What are the inputs and outputs you expect in the AND gate case?
<mithro> daveshah: I want to know when two things are logically equivalent what the timing conditions I can do the substitution
<daveshah> mithro: I still don't follow. I need an example of what you actually expect this tool to do
<mithro> daveshah: Let me draw a simple diagram
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<daveshah> mithro: yes, it seems quite far away from what Yosys does at the moment
<mithro> daveshah: So yosys does the techmapping at the moment, right?
<daveshah> mithro: yes
<daveshah> But there is no timing at all involved in that
<daveshah> And there has never really been a case where that is needed
<daveshah> Given Yosys knows nothing about routing delays, its very hard to make any timing decisions
<daveshah> They often dominate in FPGA synthesis anyway
<daveshah> I'm not convinced that in the equivalence check there is any benefit compared to conventional equivalence check plus STA
<mithro> daveshah: true -- but just because things are a certain way _today_ doesn't mean they should be that way forever more, I'm not expecting yosys to grow timing support today, or even probably any time soon - and I'm not even sure it is the right place
<daveshah> mithro: this feels more like a PAR problem than a synthesis problem
<daveshah> Yosys effectively has no idea what the delays at the A and B input would be
<mithro> daveshah: You might be right
<mithro> daveshah: First step is getting the data from the files into parameters however
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