<etrig>
why are software usb firewalls seemingly nonexistent?
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<pie_>
etrig, i dunno...write better drivers_
<pie_>
_
<pie_>
* ?
<pie_>
ok actually that was dumb
<pie_>
good question i guess?
<pie_>
i feel like they could exist, just very hard find
<mithro>
Does anyone know how to make yosys split an inout wire into an separate in and out wires? I believe its a thing that should be pretty easy to do - but can't find the right command...
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<whitequark>
iopadmap I think
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<azonenberg>
yes, iopadmap - but that also creates tristate buffer cells
<azonenberg>
So you have to have a primitive defined for doing that
<azonenberg>
etrig: because usb is below most software
<azonenberg>
firewalling it would mean a patch at the lowest levels of the kernel driver stack
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<daveshah>
rqou: congratulations!
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<whitequark>
azonenberg: doesn't even linux have a rudimentary usb firewall?
<whitequark>
you can examine device ids before letting them in
<whitequark>
sure, it doesn't help against an attacker who can plug in a configurable usb device... which is next to everyone these days...
<whitequark>
oh i think it also might allow filter devices by classes
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<daveshah>
FWIW I'm not convinced that a true "SymbiFlow" free solution should include Yosys...
<sorear>
you think it should use the old vtr builtin synthesis? or I don’t follow
<sorear>
congrats rqou
<zino>
whitequark, now I'm curious, where in the chain can you configure the usb id blocking on Linux? The points I can think of is the modprobe blacklist to prevent creating a dev node all together, or setting up some action in udev after the device node is started. Is there more?
<whitequark>
zino: yes
<whitequark>
there's a special kernel feature for that
<whitequark>
it's designed for kiosks
<zino>
Oooh. I go dig that up later. Cheers
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<etrig>
azonenberg: it's too low level? netfilter but for usb packets just isn't feasible?
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<mithro>
rqou: Good work on getting the max v to that stage - I'm still more than happy to include that work into SymbiFlow
* felix_
wonders if he missed something
<mithro>
felix_: In what regard?
<pie_>
rqou, what did i miss
<felix_>
to which stage rqou's max v project got; didn't find any recent information on that in the backlog
<mithro>
felix_: He posted on twitter
<felix_>
ah. i don't use twitter
<pie_>
ahhh
<felix_>
ooh, nice. congrats rqou
<balrog>
whitequark rqou: (offtopic) the main problem with bogus serial number for simulated Macs is that some Apple services (notable FaceTime and iMessage) will not function
<balrog>
Apple relies on serial number matching as part of their antispam efforts
<whitequark>
why would I care about FaceTime and iMessage lol
<shapr>
gotta call yr peeps?
* shapr
dunno
<awygle>
iMessage is pretty good as chat programs go but of course it's only as good as the people on it
<rqou>
mithro: ok, i will state it explicitly: i am not interested in any kind of collaboration unless you people stop with the silly embargoes
<balrog>
embargoes?
<balrog>
is this regarding xilinx 7 series?
* shapr
embargoes pickles
<elms>
rqou: Now I feel like I'm missing something, who is "you people" and what embargoes? (sorry it's not explicit to me)
<rqou>
"you people" = certain parts of the SymbiFlow team
<rqou>
and they have their own written-from-scratch place and route tool in the works that is secret because _somebody_ thinks their game of 4d chess is really goddamn clever
<rqou>
anything that's public is just a cover
<daveshah>
I must say, being part of this secret illuminati with our 4d chess PnR is great fun
<daveshah>
The initiation ceremonies are a bit weird though :P
<rqou>
go f*** yourself
<shapr>
is that part of the ceremony?
<pie_>
awygle, what :p
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<rvense>
.. that it's a mystery anybody made the web do anything before flexbox, that is
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<whitequark>
lol yeah
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<mithro>
whitequark: Do you understand the iopadmap command in Yosys?
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<mithro>
whitequark: Clifford said it might be usable to split a port into in/out but I can't figure out how and he ran away
<daveshah>
mithro: if you are using an SB_IO primitive the actual direction doesn't matter
<daveshah>
Just pretend it's an input or output
<daveshah>
Presumably all you need is a connection from the top level port io the SB_
<mithro>
daveshah: Yeah - I guess I could do that...
<daveshah>
mithro: doesn't seem any worse a hack then splitting the port really
<mithro>
daveshah: At the moment I'm hacking in a pass into yosys (gotten as far as finding all the inout ports...) -- it seems like it could be generally useful to have this feature?
<mithro>
If I manually split the in/out port, it all works on the VPR side it seems...
<daveshah>
mithro: well, it will be useful for VPR if nothing else
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<mithro>
daveshah: Well, ZipCPU was mentioning it might be useful for SAT solvers which don't support inout ports....
<daveshah>
mithro: I suppose so, but in most cases your properties would be well before the port.
<mithro>
Which is why I thought it already existed -- but it seems I was getting confused with splitting out 'z' functionality...
<daveshah>
Also most use cases I see split the port into three ports, as I think you imply
<mithro>
daveshah: Yeah the SB_IO kind of have the "three ports" in the send of a couple of inputs, couple of outputs and a "output enable" signal
<daveshah>
mithro: so yeah, I think those are the ports you would need if you want to remove the tristate inout for verification etc
<mithro>
daveshah: Do you have a way to make yosys convert the SB_IO package pin + connected stuff into just input or output ports?
<daveshah>
mithro: no, can't think of a way obviously
<daveshah>
There might be some non obvious sequence of commands though
<mithro>
daveshah: So that still leaves me at having to write a Yosys pass, right?
<daveshah>
Or modifying the primitive and then using deminout
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<openfpga-bot>
[jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fNZrU
<openfpga-bot>
jtaghal-apps/master fa45080 Andrew Zonenberg: Added libasan to jtagclient
<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 3 new commits to master: https://git.io/fNZrt
<openfpga-bot>
jtaghal-cmake/master 0dc286b Andrew Zonenberg: Enabled asan. Updated to latest submodules.
<openfpga-bot>
jtaghal-cmake/master 1d35c16 Andrew Zonenberg: Increased default warning level
<openfpga-bot>
jtaghal-cmake/master 4278a70 Andrew Zonenberg: Updated to latest logtools
<rqou>
azonenberg: why does jtaghal need asan?
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<whitequark>
rqou: what?
<whitequark>
all C++ code needs asan.
<rqou>
i thought people normally make a special build for asan
<whitequark>
well, yeah
<whitequark>
but it makes sense to always build experimental non-real-time software with asan
<azonenberg>
yeah i havent bothered tweaking the cmake scripts to have a release build yet
<azonenberg>
Since the asan build is fast enough right now
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<openfpga-bot>
[jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fNZXg
<openfpga-bot>
jtaghal-apps/master 8b160a8 Andrew Zonenberg: Fixed typo in help message
<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/fNZXV
<openfpga-bot>
jtaghal-cmake/master 83de676 Andrew Zonenberg: Updated to latest submodules
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<cr1901_modern>
whitequark: How do I define a custom unit in rink that I can use later?
<cr1901_modern>
(that lasts longer than inline unit definition)
<whitequark>
don't think you can
<whitequark>
other than by editing definitions.units
<cr1901_modern>
I see...
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<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fNZx6
<openfpga-bot>
jtaghal/master 17e36e2 Andrew Zonenberg: Added more STM32 support for lock bit testing
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