<azonenberg> awygle: i would consider "hash" to refer to any function mapping an arbitrarily long input to a relatively-uniform distribution of fixed length outputs
<azonenberg> further subdivided into cryptographic and non-cryptographic algorithms
<azonenberg> with "checksum" referring specifically to non-cryptographic hashes in which addition is the primary operation
<awygle> azonenberg: yeah i would agree with that. "small representation of big thing that hopefully doesn't collide too often"
<azonenberg> and parity being the extreme degenerate case of a checksum modulo 2
<awygle> checksum - "xor all the things" :p
<sorear> just don't call it MIC or MDC
<awygle> i don't really get the joke, except that those seem to be obsolete names for what's now called a Message Authentication Code (MAC)
<sorear> it's not a joke, more of a complaint about the amount of pre-standard terminology that is still out there
<awygle> ah
<sorear> (universal hashing is really neat and should be better known)
<awygle> what is universal hashing?
<sorear> https://en.wikipedia.org/wiki/Universal_hashing # keyed, non-cryptographic hash functions which provide guaranteed non-collision properties for any combination of inputs, as long as the key is chosen randomly and independently of the inputs
<sorear> any two messages of length 10^6 bits - if you hash them with a random irreducible CRC32, the CRCs will be the same with probability < (10^6/32)/(2^32/32)
<sorear> because the XOR difference between the messages is a degree 10^6 polynomial, which is divisible by at most 10^6/32 32-bit irreds, and you had 2^32/32 irreds to choose from
<awygle> huh. okay, cool
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale has joined ##openfpga
m_t has quit [Quit: Leaving]
azonenberg_work has joined ##openfpga
<azonenberg> awygle: so i'm almost done insulating the new place
<azonenberg> we have the HVAC turned on now, the remaining holes are small enough that i am willing to tolerate some loss of conditioned air in exchange for making that portion of the house comfortable
<qu1j0t3> i read that as "insulting the new place". maybe i am too much online
<prpplague> hehe
<awygle> azonenberg: awesome. when's the inspection?
<azonenberg> awygle: not scheduled, we'
<azonenberg> we're in full "move out ASAP" mode
<azonenberg> Lease ends... tuesday? whatever end of month is
<azonenberg> mon/tues are cleaning days
<awygle> oh damn, yes
<azonenberg> Movers are coming fri into sat
<azonenberg> sunday we're taking the last little tidbits of stuff that fits in the car
<azonenberg> So basically today was the last construction day until we're fully out of the rental
<sorear> it's not like houses are typically *supposed* to be airtight
<azonenberg> sorear: i mean i have several square meters of insulation missing
<azonenberg> its not done
<azonenberg> basically the ceiling over the 2nd floor hallway, plus a bunch of tidbits in corners and edges that are oddly shaped and need careful cutting to size
<azonenberg> awygle: it hit 125F air temp in the attic while i was working in it
<awygle> azonenberg: damn. that's no good
<azonenberg> it was bad enough that if i touched the ceiling joists with bare skin it was unpleasant
<sorear> so the W/K of your house is a little higher than it should be. this is a quantitative problem, not a categorical one
<azonenberg> the roof itself was closer to 150F
<awygle> ... how?
<azonenberg> i think i measured 147 with an ir thermometer
<awygle> it definitely did not hit 150F in kitsap
<azonenberg> on the underside of the sheathing
<awygle> i would have heard about it
<azonenberg> Lol
<sorear> is that weird? the house my parents own is *normally* 130F-140F in the attic during summer
<azonenberg> How much time do you spend in attics?
<awygle> literally zero
<awygle> i've never had one
<azonenberg> You're above the insulation
<azonenberg> with a black or dark colored roof above you
<azonenberg> limited airflow
<azonenberg> it's like a solar oven
<sorear> (measured pointing an IR thermometer at the top joists; the roof itself was usually a bit cooler)
<azonenberg> I didnt do emissivity calibration if that's what you're wondering
<azonenberg> but wood is pretty close
<sorear> hot take: roofs should not be black
<azonenberg> Not a bad idea
<azonenberg> i'd honestly be fine with like a bright reflective white :p
<azonenberg> sorear: yeah i measured about 98F at the top side of the insulation
<azonenberg> 115-125F about 2-3 fee higher on the side of a truss
<azonenberg> and 130-150F on the underside of sheathing
<azonenberg> The house itself was air conditioned, floor was in the high 60s and the "ceiling" (well, facing on the ceiling insulation - no drywall yet) was low 70s
<azonenberg> The insulation is one layer of R-38 faced fiberglass stapled to the trusses, then a second crosswise layer of unfaced R-21 fiberglass laid on top perpendicular
stefanct has quit [Remote host closed the connection]
<awygle> white roofs kill birds
<awygle> i have no idea if that's true it's just a vague belief i picked up someplace
stefanct has joined ##openfpga
<awygle> meanwhile my current apartment is making my life simultaneously better and more stressful by dropping their offer for my lease renewal such that it's still cheaper to move, but no longer a slam dunk.
<azonenberg> Lol
<azonenberg> oh, the icing on the cake
<azonenberg> We're moving the bed on saturday
<azonenberg> It's going under a tarp in the master bedroom at the new place until we hang sheetrock there
<azonenberg> I booked a month in a hotel
<azonenberg> ... starting sunday night
<awygle> .... oops.
<azonenberg> well, i booked it before we had the movers scheduled
<azonenberg> i didnt know when they were coming and i figured, sunday the lease wouldn't have ended yet
<azonenberg> so we can stay there
<awygle> time to sleep under a tarp in a non-sheetrocked room
<azonenberg> i'm thinking air mattress at the old place actually
<awygle> yeah no my suggestion was Comedy Only
<azonenberg> lol
<azonenberg> we did consider a tent in the backyard
<azonenberg> seriously
<prpplague> azonenberg: no hackaday.io project page for your new place project?
* prpplague glares at azonenberg for not sharing
<azonenberg> prpplague: I have a bunch of photos
<azonenberg> that i've mostly put on facebook, i've tweeted a few
<azonenberg> Havent taken many in the last few weeks because it was just hanging insulation, nothing exciting
<prpplague> facebook what's that?
<azonenberg> and lots of boxing up the old place
<azonenberg> Which also isnt much to show
<azonenberg> once i start setting up the new lab there will definitely be lots of pix
<azonenberg> But it's gonna be slow going since i want to do it right
<prpplague> azonenberg: i hear ya
<prpplague> azonenberg: it took me almost a year to build my lab
<azonenberg> as soon as sheetrock is up, the next step is going to be the ESD epoxy floor
<prpplague> azonenberg: lots of planning
<azonenberg> it was almost the same price as regular epoxy flooring, lol
<azonenberg> seemed silly not to ground it
<prpplague> azonenberg: yea i went with an epoxy then tiles
<azonenberg> at the moment i am not planning to tile the garage
<azonenberg> just dark-machine-gray epoxy
<azonenberg> why did you tile?
<prpplague> just didnt like the hard floor, the tiles have a but of cushion to them
<azonenberg> Just looks or did you have a practical reason?
<azonenberg> i see
<prpplague> azonenberg: nothing logical or practical, just comfort
<azonenberg> That counts as practical :p
<azonenberg> personally i am used to the hard floor so i will probably keep it
<azonenberg> my current lab has one
<azonenberg> its just ugly bc not painted
genii has quit [Remote host closed the connection]
stefanct has quit [Changing host]
stefanct has joined ##openfpga
stefanct has quit [Read error: Connection timed out]
stefanct has joined ##openfpga
stefanct has quit [Changing host]
stefanct has joined ##openfpga
stefanct has quit [Quit: quit]
stefanct has joined ##openfpga
Hamilton has joined ##openfpga
stefanct has quit [Changing host]
stefanct has joined ##openfpga
Hamilton has quit [Remote host closed the connection]
<bubble_buster> Warning: Design size of 53968 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. Expect performance to be adversely affected.
<bubble_buster> oof
<bubble_buster> I can't even get it to run for 10ns :/
stefanct has quit [Quit: quit]
<awygle> azonenberg: shocked that esd epoxy wasn't colossally expensive
unixb0y has quit [Ping timeout: 256 seconds]
unixb0y has joined ##openfpga
<azonenberg> awygle: you know what the funniest part is?
<azonenberg> of that $1K ish price i was quoted for the whole kit, bonding rods included
<azonenberg> about $600 was for the sealer to keep water vapor from going through the concrete and making the actual esd epoxy delaminate
<azonenberg> the esd epoxy itself was one of the cheaper parts of the whole quote
<awygle> The funniest part is that you paid 1k for esd flooring and didn't pay anybody to help you hang sheet rock :-P
<azonenberg> i didnt buy it yet
<azonenberg> because i dont have $1k handy
<azonenberg> Once the house is put together THEN i'm going to work on finish stuff
<awygle> Ah OK
digshadow has quit [Ping timeout: 244 seconds]
<azonenberg> (I note that i also haven't hung the sheetrock)
digshadow has joined ##openfpga
rohitksingh has joined ##openfpga
Bike has quit [Quit: Lost terminal]
wpwrak has quit [Ping timeout: 264 seconds]
rohitksingh has quit [Ping timeout: 244 seconds]
rohitksingh has joined ##openfpga
scrts has quit [Ping timeout: 255 seconds]
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
scrts has joined ##openfpga
m_w has quit [Read error: Connection reset by peer]
scrts has quit [Ping timeout: 256 seconds]
m_w has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh1 has joined ##openfpga
scrts has joined ##openfpga
rohitksingh has quit [Ping timeout: 260 seconds]
rohitksingh1 has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
pie_ has quit [Ping timeout: 248 seconds]
rohitksingh has joined ##openfpga
Hamilton has joined ##openfpga
azonenberg_work has quit [Ping timeout: 265 seconds]
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
scrts has quit [Ping timeout: 256 seconds]
m_w has quit [Ping timeout: 256 seconds]
m_w has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
scrts has joined ##openfpga
scrts has quit [Ping timeout: 264 seconds]
Hamilton has quit [Quit: Leaving]
rohitksingh has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
wpwrak has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
scrts has joined ##openfpga
scrts has quit [Ping timeout: 260 seconds]
rohitksingh has joined ##openfpga
scrts has joined ##openfpga
Miyu has joined ##openfpga
stefanct has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
wpwrak has quit [Ping timeout: 256 seconds]
keesj has quit [Ping timeout: 240 seconds]
vup has quit [Quit: The Lounge - https://thelounge.github.io]
vup has joined ##openfpga
wpwrak has joined ##openfpga
rohitksingh has joined ##openfpga
m_t has joined ##openfpga
Bike has joined ##openfpga
genii has joined ##openfpga
m_w has quit [Ping timeout: 248 seconds]
m_w has joined ##openfpga
ironsteel_ has joined ##openfpga
ironsteel has quit [Ping timeout: 240 seconds]
Miyu has quit [Ping timeout: 244 seconds]
m_w has quit [Ping timeout: 240 seconds]
m_w has joined ##openfpga
wpwrak has quit [Read error: Connection reset by peer]
wpwrak has joined ##openfpga
azonenberg_work has joined ##openfpga
<kc8apf> I was thinking about ORconf but airfare is $$$$
<daveshah> I've decided to go, will be presenting Project Trellis
azonenberg_work has quit [Ping timeout: 265 seconds]
<whitequark> daveshah: can I use the sooper sekrit fpga pnr for anything useful yet?
<whitequark> can't get this UP5K design to run at reasonable clock with arachne
<daveshah> No, it's not really beating arachne by a massive margin, right now we've focussed on features and ECP5 support
<daveshah> I think it will be circa another month before we are usefully better than arachne
<whitequark> aw
<daveshah> Carry chains seem to make FPGA placement quite a bit harder
<daveshah> I think we are now maybe 5-10% better than arachne comparing both without carries
<sorear> Roughly when does the embargo end and I can have a clue what you’re talking about?
<shapr> me tree
<shapr> three*
<daveshah> 1st August
<shapr> good to know, thanks
<sorear> Is vtr usefully better than arachne?
<daveshah> It doesn't support carries yet. Once it does I would expect it to be about 20% better maybe
<whitequark> daveshah: actually, 5-10% would be a deal breaker to me
<whitequark> because I can't pass timing by about that margin
<gruetzkopf> hitting all the weird edgecases as always
ironsteel__ has joined ##openfpga
ironsteel_ has quit [Ping timeout: 260 seconds]
azonenberg_work has joined ##openfpga
<whitequark> maybe I should just not run icetime
pie_ has joined ##openfpga
<whitequark> ok well, this needs either an FPGA that isn't shit or tooling that isn't shit
<openfpga-github> Glasgow/smia 282d894 whitequark: applet.smia: new (partially functional) applet.
<openfpga-github> Glasgow/smia 2e1c627 whitequark: Use correct form of %#0Dx format specified....
<openfpga-github> [Glasgow] whitequark created smia (+2 new commits): https://github.com/whitequark/Glasgow/compare/2e1c62749780^...282d8940b55e
<openfpga-github> [Glasgow] whitequark fast-forwarded master from 5665ad6 to 2e1c627: https://github.com/whitequark/Glasgow/compare/5665ad658066...2e1c62749780
<daveshah> I hope both will come together soon with the ecp5 work
<whitequark> no, I mean, HX8K works here.
<daveshah> Yeah
<daveshah> I wish Lattice would make a up5k with hx timings
<awygle> daveshah: i am sure i've asked you this before but is Ultra faster than UltraPlus?
<daveshah> awygle: I don't think so, but I can't remember whether I actually looked at it
<daveshah> Seems the same based on the indicative timing numbers in the datasheet
<kc8apf> daveshah: you inspired me to submit a talk to ORconf on 7-series
<daveshah> kc8apf: Awesome!
<awygle> this external dependency has an obvious bug and a test suite that doesn't even compile let alone run and pass
<awygle> i was about to go all whitequark on them and fix their shit but turns out the project is abandoned
<awygle> now i have nowhere to vent this irritation so it ends up on irc
<qu1j0t3> ^ relateable
<awygle> also i probably maintain this dependency forever now unless i can find a replacement
rohitksingh has quit [Quit: Leaving.]
m_w has quit [Ping timeout: 264 seconds]
m_w has joined ##openfpga
pie_ has quit [Read error: Connection reset by peer]
pie__ has joined ##openfpga
pie__ has quit [Remote host closed the connection]
<awygle> oo, daisho on the ecp5
<awygle> tinyfpga: will you support USB 2 as well as USB 3?
<openfpga-github> [Glasgow] whitequark pushed 2 new commits to master: https://github.com/whitequark/Glasgow/compare/2e1c62749780...5290d502419a
<openfpga-github> Glasgow/master 5290d50 whitequark: applet.i2c.eeprom_24c: rename, add proper user interface....
<openfpga-github> Glasgow/master d6883a6 whitequark: applet.i2c_master: allow transactions of up to 65535 bytes in size.
<tinyfpga> awygle: Full speed works with the bootloader
<tinyfpga> awygle: not sure how much time if any that I will spend on the USB2 Daisho Fire
<tinyfpga> *core
<awygle> ah ok
<tinyfpga> awygle: you don’t really need a USB2 device for USB3 to work
<awygle> tinyfpga: i have a use case for high-speed USB 2 lol. USB 3 is also cool but i don't have an immediate use case personally
<tinyfpga> awygle: USB2 requires an external phy
<awygle> tinyfpga: yes, i know, although i've never dug in deep enough to figure out why exactly
<tinyfpga> awygle: for 480mbit/s high speed
<tinyfpga> awygle: it’s because USB3, SATA, PCIE, NVME, and a few others use a very similar physical interface
<tinyfpga> awygle: so phys tend to be easier to make and more common for those as a while
<tinyfpga> awygle: while USB2 high speed is a whole different matter. Someone might be able to make it work, but it’s tricky
<daveshah> I am planning to add ULPI PHYs to my future may never happen ECP5 board
<daveshah> I believe USB2 using pins, if even possible, will require at least 4 IO because you have to have both SE and diff IO
<daveshah> But I may be wrong. I also suspect clock recovery will be quite tricky, and if not space constrained a ULPI Phy is well worth the dollar
<awygle> even if space constrained honestly. cypress makes a 3.75mm^2 ulpi phy
<daveshah> I'm thinking of space constrained in the tinyfpga sense :P
<tinyfpga> XD
<awygle> even tinyfpga can afford 4 square millimeters lol. although those pictures of the EX really brought home how squeezed you are to fit on that board
<awygle> i didn't realize the FPGA was quite so... interdigitated with the header pin holes lol
<whitequark> USB 3 Glasgow will just use a Cypress chip to not bother with any of this :D
<whitequark> awygle: btw I realized one thing I want on revC
<whitequark> two differential lanes
<balrog> whitequark: how would you do a usb3 glasgow?
<whitequark> one of them clock-capable
<whitequark> what connector would be best for that? I'm thinking mini-HDMI
<whitequark> balrog: same general principle
<whitequark> Cypress FX3 + Lattice ECP5
<whitequark> I'm just going to iterate on the current design until it stops working completely
<whitequark> I really like how I don't need to re-synthesize and re-PAR the USB core with the current design
<awygle> whitequark: usb-c, mini-hdmi, mini-display port, SATA all come to mind. how fast are you thinking?
<whitequark> awygle: well UP5K is limited to like 30 MHz
<whitequark> HX8K -might- be able to do like 100 MHz DDR
<whitequark> USB-C is bad since we are using (or may be using) that for the host interface, so it's out
<whitequark> SATA is huuuuge
<azonenberg_work> whitequark: u.fl?
<azonenberg_work> :p
<awygle> mk. are you thinking more capable sync, or what?
<azonenberg_work> q-strip?
<awygle> azonenberg_work: bite your tongue
<azonenberg_work> mmcx?
<daveshah> mini hdmi seems like a good compromise to me
<whitequark> awygle: well I tried to connect a SMIA camera
<azonenberg_work> (that last is a serious suggestion)
<whitequark> it uses SubLVDS
<whitequark> so I had to dig out an HX8K devboard to use solely as a SubLVDS receiver and convert it to single-ended
<whitequark> that's next to a tristate buffer I use for I2C
<whitequark> I2C will be fixed in revC, the other bodge should be fixed too, I think
<whitequark> a real good question is what sort of buffer will go there
<whitequark> unless we can dedicate an FPGA I/O bank to LVDS
<whitequark> which could be an option, really
<awygle> so you just want to hook up *LVDS to $arbitrary_serial_lvds_interface on a DUT?
<whitequark> basically
<awygle> welllll we do have another bank available on the HX
<daveshah> Only bank 3 on the hx does lvds iirc
<whitequark> yes
<whitequark> well, has native LVDS inputs
<daveshah> yeah
<whitequark> awygle: so we have a complete 24Cxx EEPROM applet now
<whitequark> I've reflashed a few devices already
<whitequark> right now looking at some random broadband modem
<whitequark> see, thinkpads have PCI ID whitelists...
<gruetzkopf> ah, my favourite trick :D
<awygle> lol that sounds like fun
<gruetzkopf> (my dell equivalent laptop is whitelist free)
<whitequark> I've pretty much desoldered everyting I found in the junk pile here and am connecting it to Glasgow
<whitequark> this results in quite a few applets, though only some of them reach production quality
<whitequark> the I2C one is pretty reliable now
<whitequark> I'm quite amazed honestly just how easy it turns out to be, microcontrollers are -way- harder than this
<awygle> whitequark: so, this is not a position i'm advocating, but these are interesting test results showing .1" headers having reasonable insertion loss out to something like 4 GHz http://suddendocs.samtec.com/testreports/hsc-report_tsm-04_hle-02_web.pdf
<whitequark> you never get "just a good fat FIFO to the host" with them
<whitequark> huh
<whitequark> that's... interesting
<awygle> now that's not over a cable and it's mating Samtec to Samtec board-to-board, so close to an ideal case. but yeah. interesting.
<whitequark> it just feels so gross
<awygle> it does lol. but without a standard pretty-high-speed LVDS connector on the DUT side i'm always going to feel gross about it :/
<whitequark> right
<whitequark> another thing I'm thinking about here btw is a standard set of breakout boards
<whitequark> something you might get on ebay using a "smd breakout board" query but better
<awygle> interesting. that would be very useful
<whitequark> I'm thinking go over top 50 most used connectors in kicad and make a board from that to Glasgow 0.1"
<whitequark> because the amount of 0.12mm² PTFE-coated wire in my life has recently exceeded all reasnable limits
<whitequark> I just soldered USB and power to a mini-PCI-e socket I desoldered from some random motherboard, put the modem in, and put the assembly in a -vise- so that spring-loaded contacts have, well, contact
<whitequark> this looks disgusting
<whitequark> it does work
<whitequark> awygle: also idea
<awygle> lol @ vise
<whitequark> breakout boards with >>16 contacts that have a small FPGA on them that only serves the purpose of routing
<whitequark> maybe even CPLD
<whitequark> but better an iCE40 FPGA because we are guaranteed to have a toolchain for that
<whitequark> see, I realized that I can -very- easily add aux FPGAs to applets because I already have (a) migen, (b) icestorm, (c) program-ice40 applet
<whitequark> and applets can call other applets, though it's not very elegant right now
<awygle> whitequark: if we wanted to take a "thou shalt use a breakout board" position for rev C, we could use something like a QTH (60 pins and a ground blade) to run 2 single-ended ports and a differential port up to the breakout board and then do The Right Thing there, connector-wise
<whitequark> I also have an abstraction layer for pins already, so you could, in principle, specify pins as they are on the breakout board, and Glasgow host software would generate and load an aux bitstream
<whitequark> hmmm
<awygle> idk how the fpga pins work out for that but i bet it's fine, HX ports are big
<whitequark> I feel like QTH is "rev D material"
<whitequark> there's certain simplicity in 0.1" headers
<awygle> could be (although it'd probably be a 90+ pin version)
<whitequark> if we go the QTH route then we should not put any level shifters on the main board itself
<whitequark> only TVS diodes
<whitequark> not sure, this increases the cost quite a bit, and complexity too. definitely not rev C
<awygle> totally fair. i think those two options kind of bracket the search space.
<awygle> "all 100-mil all the time" and "fancy high-speed mezzanine connector"
<whitequark> right
<whitequark> I do think routing out bank 3, maybe even with its own DAC/LDO, to a non-buffered 0.1" header is a good idea; it would be like "using this voids your warranty, make sure you know what you're doing"
<whitequark> might not even populate it out of the box
<awygle> yeah agreed. although azonenberg_work might have some kind of LVDS level shifter part number sitting on the tip of his tongue.
<whitequark> there's definitely use cases where you absolutely positively do not want level shifters in data path
<azonenberg_work> awygle: Loooool
<azonenberg_work> qth from glasgow to level shifter board?
<azonenberg_work> you are literally reinventing starshipraider right down to exact component choices
<azonenberg_work> My IO card slot is a QTH-030 with 8x LVDS inputs, 8x LVCMOS33 outputs, 8x LVCMOS33 output enables
<azonenberg_work> plus I2C, power, and a bit of miscellaneous stuff
<azonenberg_work> I don't even have TVS's on the main board
<azonenberg_work> all io protection and/or level shifting is pushed to the output
<awygle> yeah yeah. everybody loves QTH lol
<awygle> "you ALSO picked the best high-speed board to board connector? shocking!" :p
<azonenberg_work> lol
<azonenberg_work> i just think it's funny how much these designs are converging
<azonenberg_work> If you *do* move to q-strip i'd suggest you guys consider using a compatible pinout
<Adluc> azonenberg_work: do you follow any conventions for pinouts or just as it comes?
<azonenberg_work> Adluc: Generally speaking i put power and gruond at the ends
<azonenberg_work> ground*
<azonenberg_work> i use the xilinx 2mm 2x7 jtag as my standard jtag connection no matter what the actual device being used is
<azonenberg_work> For low speed GPIO i like pmod-compatible
<awygle> azonenberg_work: so _do_ you have an LVDS-capable SN74LVC1T45 equivalent?
<awygle> i mean that part could presumably work as-is but it's not really the intended use case
<azonenberg_work> just a buffer, or what?
<azonenberg_work> lvds to single ended?
<azonenberg_work> how fast?
<awygle> i was thinking LVDS-to-LVDS dual supply
<awygle> but maybe that's like... not a thing
<azonenberg_work> what is the point?
<azonenberg_work> its LVDS at both ends, same voltage level
<azonenberg_work> Or do you want a repeater/buffer, not a converter?
<awygle> i'm using LVDS here loosely, not strictly
<awygle> "fast differential signal"
<azonenberg_work> "anything fast differential" -> LVDS
<azonenberg_work> i used this on a client design some years back for i think LVPECL -> LVDS
<awygle> hm, interesting. definitely worth keeping around.
<whitequark> yeah
* awygle returns to paid work
Bike has quit [Ping timeout: 252 seconds]
<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/5290d502419a...74a7e8d6a071
<openfpga-github> Glasgow/master 74a7e8d whitequark: applet.i2c_master: implement bus scanning.
<openfpga-github> Glasgow/master 0294e3a whitequark: cli: use colors when logging to a TTY.
<openfpga-github> Glasgow/master 89469d3 whitequark: cli: use {-style format strings.
Bike has joined ##openfpga
<openfpga-bot> [jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fNzx0
<openfpga-bot> jtaghal/master 4b27604 Andrew Zonenberg: Added write-memory function to DebuggableDevice
<openfpga-bot> [jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fNzxu
<openfpga-bot> jtaghal-apps/master 4de10bf Andrew Zonenberg: Implemented debug-writemem command
<rqou> damn this is frustrating
<rqou> red team at $WORK has just been failing over and over
azonenberg_work has quit [Ping timeout: 256 seconds]