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<balrog> what's this SYCL thing?
<balrog> looks like some C++ variant
<rqou> azonenberg, awygle: ping?
<rqou> can i get a mini-design review of this section:
<rqou> having gnd/power planes is so nice
<awygle> Lol yes
<rqou> also, exposed-pad QFPs are _awful_
<rqou> the exposed pad gets in the way of everything
<awygle> Nothing looks inherently bad here. I might spread traces more where you have room.
<awygle> Anything in particular you're worried about?
<rqou> nah, this is just the first time i actually did a "hmm, maybe signal integrity matters" layout
<awygle> And yes thermal pads are the worst
<awygle> Your usb isn't length matched
<rqou> it's not even for high power dissipation
<awygle> Is it impedance matched?
<rqou> it's just for "ran out of pads"
<rqou> should be impedance matched
<rqou> idk how much length matching matters here?
<awygle> Not a lot, it's just the "right thing"
<awygle> You can't be mismatched by much
<awygle> Red-G-P-Blue stack up?
<rqou> red-purple-orange-blue
<rqou> but purple is just a solid plane so you can't see anything
<awygle> What's the weird blue T?
<awygle> Under the small qfp
<rqou> regulated vout from the ftdi chip that then goes through two filters to become Vphy and Vpll
<awygle> Ah that's K then. I might do a pour or fatten the traces but it's unlikely to matter.
<awygle> Should fatten the red trace to 5V tho
<rqou> for inductance?
<awygle> And just resistance. I'm taking about the one that goes to your orange 5v trace
<rqou> i mean, it all has to feed through the tiny usb micro pad
<rqou> but ok, i will
<rqou> this layout isn't 100% final yet
<awygle> It adds up though, it's not "skinniest bit wins"
<awygle> Otherwise it looks really good. Pin swapping was kind to you lol
<rqou> is it normally not for you? :P
<awygle> I am still pretty new to FPGAs where all pins are interchangeable lol
<awygle> Analog is a lot less flexible
<awygle> Speaking of is interesting. Not exactly the answer to your decoupling question but still useful.
<awygle> I love return current density simulations over frequency
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<rqou> azonenberg, awygle: how's my decoupling?
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<awygle> rqou: try to avoid sharing vias if you can
<awygle> (not the end of the world if you can't though)
<rqou> seems a bit tricky here
<awygle> Otherwise looks fine to me (without looking at the schematic or the pinout)
<awygle> I was mostly looking at the top left, seems room for a second ground via
<rqou> ok, i'll think about it
<awygle> beyond decoupling, a via for each gnd ball is preferred too
<awygle> But ultimately nbd here I suspext
* awygle zzz
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<pie__> hm
<pie__> <feep> > BTW, if you are operating a data center, NVIDIA has recently updated their EULA to prohibit “desktop” grade GeForce and Titan GPUs from being used in data centers.
<pie__> <feep> they're finally at a point where they can somewhat reliably clock cards to full
<pie__> <feep> shouldn't google put a team on nouveau?
<pie__> <feep> so
<pie__> <feep> the eula only covers the driver
<pie__> <feep> I wonder to what extent the use of driver lockout to make devices act as software for licensing purposes is illegal
<rqou> i don't get why reclocking has been so hard to figure out
<pie__> though now its got me wondering about gpu computation error rate
<pie__> googling hpc gpu error rate gives some decent looking results
<pie__> apparenly gpus with ECC ram is a thing
<pie__> makes sense i guess.
<azonenberg> yeah any tesla card will have ecc
<azonenberg> idk about quadros
<azonenberg> quadros are designed for rendering, teslas are pure compute
<azonenberg> most of them dont even have video out connectors
<rqou> o/ azonenberg
<rqou> why are you so intermittently responsive?
<pie__> > family man doing family things
<azonenberg> rqou: busy doing construction, then $sidegig
<rqou> how done is construction?
<azonenberg> Framed out the access door for the attic in the lab today
<azonenberg> Framed the wall under the stairs
<azonenberg> Insulated that wall
<azonenberg> Framed out the wall around the water main in the lab
<azonenberg> Insulated that wall
<azonenberg> Insulated all but about the last 4 feet of the lab ceiling
<azonenberg> and a few other odds and ends
<rqou> how come your "misc list" seems to be unending
<azonenberg> Because new things keep being added to it :p
<azonenberg> Tomorrow's goal is to finish insulating the last bit of the lab, then insulate the ceiling over the kitchen, dining room, and bathroom upstairs
<azonenberg> Stretch goal is to do some of the bedrooms too
<azonenberg> that may have to wait until monday over lunchtime / after work
<azonenberg> rqou: but most of these items had been on the todo for a long time
<azonenberg> The wall around the water main actually got rebuilt today in a slimmer fashion, my original design stuck out too much and the electrical inspector didnt like it
<azonenberg> so now i'm tighter to the concrete
<azonenberg> all of the other stuff had been pending for weeks and i just now got around to it
<azonenberg> Sheetrock arrives monday so my focus right now is doing easy things that use up bulk quantities of materials, like insulating the ceiling
<azonenberg> to free up space on the floors for the sheetrock
<rqou> when i was helping you a whole month ago, i was under the impression that you would be imminently done
<rqou> due to getting kicked out
<cr1901_modern> >azonenberg: Because new things keep being added to it :p
<cr1901_modern> Story of my life. This is why I'm refusing to add any more entries until a few old ones are done. It's... actually been quite effective
<azonenberg> i'm working as fast as i can
<azonenberg> And no faster
<rqou> and in reality you weren't even _close_?!
<azonenberg> Nope
<azonenberg> we had 2+ weeks of electrical
<azonenberg> after that
<azonenberg> then insulation came a week or two ago, at this point we've done the majority of the walls and somewhere between a third and a half of the ceilings
<azonenberg> Ceilings go a lot quicker than walls, for the most part, because there's less obstacles in the way
<azonenberg> A lot of the wall cavities are partial height... the second floor is a few inches shorter than 8 feet because that was the style in the 70s
<azonenberg> the first floor has a lot of split areas around the foundation where you have a top and bottom piece
<azonenberg> so almost every piece had to be cut to length
<azonenberg> a lot of studs are doubled or spaced around windows so you have to adjust width too
<azonenberg> then you need cutouts for electrical boxes etc
<azonenberg> meanwhile the ceiling cavities, for the most part, are exactly 2 feet wide everywhere and have relatively few electrical boxes to dodge
<rqou> at the pace you're going i see no way you'll be done by the end of this year, let alone by your mandatory deadline
<azonenberg> Then the second layer of insulation in the attic is just laid loosely on top
<azonenberg> oh and we've been moving a carload of boxes every day we go over to do work
<azonenberg> and just staging them in random corners of rooms that are insulated already
<azonenberg> so we have less to move at EOM
<azonenberg> And well, at this point there isnt a whole ton left
<azonenberg> I have to frame dummy walls in two closets downstairs to hold insulation (maybe 2-foot long walls, should be like 3 studs each)
<azonenberg> put one or two extra ceiling joists in a closet around a HVAC duct
<azonenberg> put a few 2x4s around the HVAC in the office
<azonenberg> Install a handful of insulation bits downstairs, but the first floor is almost done
<azonenberg> Hang a bunch of insulation in the walls upstairs, almost all of these pieces are precut by ally while i was at work and just have to be hung
<rqou> this list is absolutely no shorter than the "just" list from a month ago
<azonenberg> Insulate the remainder of the second floor ceiling
<azonenberg> Then hang sheetrock and do finish electrical
<azonenberg> and well, as i get closer to various items they get split
<azonenberg> "hang insulation" was one item a month ago
<azonenberg> now it's like 30 tiny items
<azonenberg> Because when something is a long way out it's hard to know all the steps
<azonenberg> As soon as sheetrock arrives, i can start working on sheetrocking the interior (non-insulated) wall and ceiling areas downstairs
<azonenberg> in parallel with the insulation
<azonenberg> Since the inspector only needs to see the insulation in the walls that, well, have insulation in them
<azonenberg> nothing is stopping me from sheetrocking the rest
<azonenberg> i might try and pull some sar folks for a work party, thats a community i havent begged for help yet :p
<pie__> amish style
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<azonenberg> rqou: in any case, progress is being made and that's all i can say
<azonenberg> I'm confident i will have insulation done in a couple more days, sheetrocking will most likely not be done on time but i can always hope
<azonenberg> If we end up couch surfing for a bit, or sleeping on an air mattress on the deck or something, we'll deal with it
<rqou> i'm going to predict that you won't be done even by december
<azonenberg> Define "done"
<azonenberg> insulation in, sheetrock up, power turned on?
<azonenberg> there's a nontrivial chance that we'll slip the deadline by a week or two but certainly end of august i have no doubt
<azonenberg> But that's when all of the other work starts
<azonenberg> new roof (not much to do from our perspective there except sign the check), sanding and painting the walls, trim, flooring
<azonenberg> ESD floor in the lab
<azonenberg> buy and install the UPS
<azonenberg> pull data lines through all the conduits
<azonenberg> Measure the conduits and pull fiber
<azonenberg> buying and installing cabinets and shelving
<azonenberg> some new workbenches probably
<azonenberg> hiring folks to put exhaust fans and HVAC in the lab
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<azonenberg> installing the racks properly, bolted to the floor etc
<rqou> fine, i'm defining "done" as "able and willing to contribute to openfpga again"
<azonenberg> Oh
<rqou> i'm going to estimate this at january 2019 at the rate you're going
<azonenberg> you do realize we are going to be remodeling the kitchen and both bathrooms too right?
<azonenberg> this whole renovation we've been doing is only the initial stages
<azonenberg> literally just enough to get the place livable
<azonenberg> we have several years more work to do
<azonenberg> that being said, as soon as we're moved in and i have a minimum viable lab put together in whatever corner of one room is somewhat clean
<azonenberg> the pace of work will slow down drastically since we wont be under a time crunch
<rqou> wtf
<azonenberg> Which means the work will be taking much longer, but it won't be dominating my schedule like it does now
<rqou> fine, my new revised estimate for done is now january 2025
<azonenberg> i'll be spending a few hours here and there on it while doing other stuff too
<azonenberg> Also, we were and continue to be budget limited in addition to time limited
<rqou> your renovation has already been taking ludicrously long
<azonenberg> So for example, when the new roof is going up
<azonenberg> and during the weeks prior
<azonenberg> i expect to be doing almost no other construction as we wont be able to afford any other materials
<azonenberg> Ludicrously long? look at how many man-weeks it takes to build a house normally
<azonenberg> now imagine about 1.2 people doing all that work
<azonenberg> (i dont count ally as a full person because of her relative lack of experience, she's not nearly as fast as an experienced construction laborer)
<azonenberg> i'm surprised its getting done as fast as it is
<cr1901_modern> That's still mean lol
<azonenberg> But yeah, from my perspective the immediate goal is to get the place to the point that it's legally occupiable
<azonenberg> That means all insulation up and inspected, sheetrock hung with one coat of mud over the tape, and all electrical fixtures installed and inspected
<azonenberg> goal is end of month, failing that as quickly as possible
<pie__> #occupyazonenberg
<azonenberg> After that i'm probably going to take a weekend to do... anything but construction
<azonenberg> lol
<azonenberg> after that, start working on all of the finish stuff
<azonenberg> Which as i mentioned i full expect to run into next year
<azonenberg> My lab will probably be largely offline for six or more months
<azonenberg> this was the case with my last move too, and one of the reasons i hate moving
<azonenberg> unpacking bit by bit, upgrading gear as i go
<azonenberg> as part of the lab revamp for example i'm getting a curie point soldering iron
<azonenberg> But not until i can afford one
<azonenberg> i may not bother to set up the old aoyue POS
<rqou> i'm still sticking to 2025 as my estimate for when you'll actually start working on openfpga again
<rqou> given just how slow everything's been going
<rqou> you should seriously just hire some illegal immigrants or whatever to help you
<azonenberg> i expect to be spending a lot of time post-move on $sidegig stuff trying to bring in cash to fund both the renovations in general
<azonenberg> and new lab equipment
<azonenberg> before i settle in and start actually using said lab
<azonenberg> i have probably $30-50K of upgrades i want to make to the lab alone once the construction proper is done
<azonenberg> $8K of UPS, $5K or so of HVAC, $1K of soldering iron, a few $k of benches and shelving
<azonenberg> $13K of 1 GHz DSO
<azonenberg> this is my first time actually outfitting a lab for the long haul, rather than "hack something together to use until i move again"
<azonenberg> So i'm doing it right
<azonenberg> But i'm also not going to rush it just so i can work on some project right now
<rqou> hey azonenberg, have you ever considered the fact that, despite not paying your bills, there are many people who would really love to see your open-source contributions?
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<azonenberg> i'd love to have 40 hours a day to work on things
<azonenberg> but i dont
<azonenberg> and i have to prioritize
<azonenberg> i'm in this for the long haul, investing in facilities that i'll be using for decades
<azonenberg> Once i get back up and running, LATENTRED is the next priority so i can get a 10G LAN
<azonenberg> STARSHIPRAIDER is now a priority at work, so i'll be doing that by day as time permits
<azonenberg> they're funding me to work on jtaghal now too
<azonenberg> i have scopehal/scopeclient building under cmake and will be adding a bunch of decoders for my $dayjob research
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<azonenberg> So its not like i'm not doing open source work at all
<azonenberg> But i have to focus on things that pay the bills
<azonenberg> jtaghal is going to be getting a lot more arm coresight support over the coming weeks
<azonenberg> and probably some stm32 stuff
<azonenberg> scopehal is going to be getting a jtag protocol decoder to test all of this
<azonenberg> (and to help with REing proprietary jtag tools)
<azonenberg> among other things, as per twitter, i want to RE the chipscope jtag protocol
<azonenberg> and make a scopehal backend to talk to chipscope cores
<azonenberg> in addition to redtin
<rqou> hmm, none of these are projects that i'm particularly interested in
<rqou> i'd be much more interested in for example homecmos
<azonenberg> yes, thats a long term project which requires substantial physical infrastructure
<azonenberg> Like the $3k+ fume hood i dont yet have
<azonenberg> or the glove box i might not even have a place to put
<azonenberg> You see why i'm making infrastructure my priority right now?
<azonenberg> i have to do the whole house to start so it's livable, but once we're moved in focus will shift towards outfitting the lab properly
<rqou> or you can do it hackily
<rqou> idk, i always find the specific way you prioritize things to be really weird
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<rqou> azonenberg, awygle: can i get a quick design review?
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<gruetzkopf> doing infrastructure work when stuff is in the way is incredibly annoying
<gruetzkopf> that said, a friend and i did the whole "normal electrical" side of a 3 story building in about 4 days
<gruetzkopf> the 60VDC/funny voltages AC/100Hz AC stuff took another week
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<sorear> azonenberg: did you just say you *are* experienced as a construction laborer
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<pie__> sorear, he probably is now XD
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<mithro> daveshah: ping?
<daveshah> mithro: just eating dinner. be with you in 15 mins
<mithro> daveshah: Okay, no huge hurry
<sorear> over here most “3 story buildings” are houses :D
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<gruetzkopf> specialised commercial building
<gruetzkopf> the upper level of the lower part of the building contains contains an object-oriented relay-based railway interlocking system, consisting of ~7500ish relays
<sorear> How large of a geographical area is it responsible for?
<daveshah> mithro: pong
<pie__> "object-oriented relay-based railway interlocking system"
<pie__> >"object oriented"
<pie__> >"relay based"
<pie__> i think im misunderstanding something here xD
<daveshah> Chatting a few years ago with a friend who worked on railway systems, new signalling products were being created running something like Visual Basic 3 (way before .NET anyway) on Windows XP...
<daveshah> It is probably one of the most conservative industries
<gruetzkopf> nope, you're not
<gruetzkopf> with this tech you can do 6.5 km in all directions
<sorear> How many signals are there in that radius?
<gruetzkopf> pretty much as many as you want. minimalistic config would be around 12, including distant signals, in our case its 50-ish, if you look at cologne central station it's a lot more
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<gruetzkopf> our setup is for development purposes, we're not actually controlling the railway line once controller from that building
<sorear> That’s a big and expensive building for 12 signals?
<gruetzkopf> tiny setups would have smaller buildings, of course
<gruetzkopf> our setup is 6 rows of 5 frames of relays, ~50ish signals, 2 level crossings, 38 points, 4 lines on either end
<gruetzkopf> the minimal case would be 4 frames for a simple crossing on a single track
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<mithro> Would people recognize these as a FF verse a latch?
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<daveshah> mithro: I suppose so, but personally I think a letter E would be clearer
<mithro> This is what my theme looks like currently
<mithro> bblr, going to find some brunch
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<mithro> daveshah: Would you say this is better?
<daveshah> mithro: yeah
<mithro> I feel like the D/Q don't line up because of the q bit below the text line
<daveshah> Think it will be OK once pins are added
<daveshah> Personally I'd remove the pulse symbol from the latch, but I'm OK with it too
<mithro> daveshah: I know without the pulse symbol it will confuse future Tim because he will mistake it for a FF
<daveshah> mithro: sure
<mithro> daveshah: I'm pondering if I should just put the word "latch" on it
<daveshah> mithro: yeah, they're not really that common anyway
<daveshah> I know 7 series has them, ice40 and ecp5 don't
<Adluc> Hello guys, although obscure question, but does anyone have any beckhoff/ethercat stuff IP cores?
<mithro> The ice40 has them in one place - the "iCE gate latch" which is how I ended up down this rat hole
<mithro> daveshah: any idea why latches are so uncommon?
<daveshah> mithro: there are many reasons why clocked logic is a better solution
<daveshah> More predictable timing and no problem with glitches
<daveshah> FPGA logic synthesis is not glitch free, which causes problems with anything asynchronous
<mithro> daveshah: Also, Clifford mentioned that we should probably just be comparing the output of a simulator before and after pnr rather than trying to logic equivalence checking for things like blinky
<daveshah> mithro: yeah, I think I mentioned that a while back
<daveshah> For slow stuff like blinky simulation is definitely the correct approach
<daveshah> For stuff which only needs a few clocks to do stuff, verification should also be good
<mithro> daveshah: except that requires having an actual testbench, or do you think we can get away with the sim command in yosys?
<daveshah> mithro: or use Verilator and dash off a quick C++ testbench
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<mithro> daveshah: Run time isn't the issue - it's me writing verilog :-)
<daveshah> mithro: exactly, that's why I suggested writing C++ instead
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<mithro> How does one control the iverilog output vcd filename?
<daveshah> I think that would normally be in your dumpvars statement
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<kc8apf> Adluc: I looked a few months ago and couldn't find any. The specs are only available to businesses in the automation industry or for purchase through IEC.
<kc8apf> Physical and link layer seems straightforward. I have no idea what the routing layer looks like other than slots in a process data packet.
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<mithro> daveshah: I'd like to pass it in on the command line... I thought I could do this with a -DVCDFILE="blah" but I'm getting "Unable to bind wire/reg/memory `VCDFILE' in `test'"
<mithro> But my -D isn't being passed through to the preprocessor from what I can see
<mithro> I'm obviously doing something wrong but I can't figure out what :-/
<reportingsjr> esden: ping
<daveshah> mithro: missing a backtick before VCDFILE in the Verilog?
<daveshah> Classic mistake coming from C/C++ to Verilog
<daveshah> mithro: should be $dumpfile(`VCDFILE)
<mithro> daveshah: the "$dumpfile(VCDFILE);" should be "$dumpfile(`VCDFILE);" ?
<daveshah> mithro: yeap
<mithro> daveshah: Hrm, that is making iverilog say "syntax error" on that line now...
<daveshah> mithro: are you passing it on the command line? It could be that command line defines lose the quotes for some reason
<daveshah> You can always use -E to see the preprocessor output
<mithro> daveshah: Ahh ha
<daveshah> mithro: escaping the quotes on the command line like \" should work
<mithro> daveshah: Yeah - that seems to make it work...
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<daveshah> mithro: AFAIK it is bash that eats the quotes. So escape may not be needed in a Makefile, fwiw
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<qu1j0t3> also watch that $ is special in a Makefile so for a literal $ you must double it
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<mithro> You really do need a *lot* of clock ticks to make blinky have an output effect
<daveshah> mithro: yeah
<daveshah> Humans are very slow compared to FPGAs :P
<mithro> daveshah: I feel like the simulator is a bit slow though... it seems like this should be pretty easy to simulate :-)
<daveshah> mithro: yeah, try Verilator
<daveshah> Writing the VCD file, depending on what you dump, will be quite slow too
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<mithro> daveshah: I'm just making the blinky take a "clock mhz" define and will set it something much smaller for simulation
<daveshah> mithro: yeah, makes sense
<mithro> daveshah: Also means we can make things blink at ~similar speeds on different boards :-)
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<mithro> daveshah: Hrm -- $value$plusargs("vcd=%s", vcdfile)
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<mithro> daveshah: Just confirming -- this looks wrong right?
<mithro> Specifically the line 12 and line 50....
<daveshah> mithro: yeah
<daveshah> I'd say so
<mithro> daveshah: So this is simulating *before* doing PNR....
<daveshah> mithro: weird
<daveshah> You mean on the Yosys output?
<mithro> daveshah: I mean the verilog - untouched via yosys / etc
<daveshah> mithro: does index look sensible?
<daveshah> tbh my next step would be to check in Vivado or something to rule out a problem in Icarus
<mithro> daveshah: Probably something I have done to the verilog
<daveshah> mithro: it could be a simulation weirdness like a race condition or uninitialised values
<daveshah> But I'd definitely cross check with another sim to be sure before wasting too much time
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<daveshah> mithro: maybe ZipCPU is around, is more his field than mine and a better timezone too
<mithro> daveshah: Looks like it's actually just something to do with the escaping of names...
<mithro> daveshah: Well, I think I have a testbench output vcd I can possibly use to diff against the .bit verilog...
<daveshah> mithro: I don't think that will necessarily work, because of Xs and potentially different netnames
<daveshah> A proper test bench that prints the valid output of checker, for example, seems better
<daveshah> Then it's effectively just one value to check
<mithro> daveshah: Hrm? Now that the testbench seems to be working, I'm only recording the top level names now
<daveshah> mithro: yeah, but there may still be a difference
<mithro> What type of difference are you expecting?
<daveshah> Registers tend to start at X in a simulation and 0 in hardware/icebox_vlog
<daveshah> If you make them all 0 in simulation I think you will be OK
<mithro> Hrm - turns out the name "checker" might be a bad choice - "Lexer warning: The SystemVerilog keyword `checker'"
<rqou> awygle, azonenberg: ping?
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