<rqou> azonenberg: so, thoughts on sticking with 0.1 uF vs switching to 4.7/0.47?
<rqou> azonenberg: why doesn't the xc2 dev board have 10uf/4.7uf caps on each chip?
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<gruetzkopf> 2.028MHz is OBVIOUSLY ISDN E1 bitclock ;)
<gruetzkopf> *2.048
<rqou> lol
<rqou> what is up with you europeans and your obsession with E1?
<rqou> afaict here nobody really cares about T1
<rqou> it's weird and obscure if you don't do "telco stuff"
<jn__> plot twist: gruetzkopf does telco stuff sometimes
<rqou> wow, this jtag mux uses a _ton_ of pins
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<rqou> is the de-facto "herp derp low-speed" interface for programmable logic dev boards still PMOD?
<awygle> Yep
<rqou> i love (/s) how we have so many mutually-incompatible standards
<jn__> <relevant xkcd>
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<awygle> Under what circumstances are the terms "data plane" and "control plane" appropriate to use?
<rqou> i see it a lot when discussing networking equipment
<rqou> argh, electrical engineering is teh hardz
<rqou> how the fuck do people manage to meet the usb inrush current limit?
<rqou> (inb4 "they don't")
<awygle> I mean they don't, and/or they use less capacitance.
<rqou> awygle: does glasgow have a ferrite bead on the usb?
<rqou> azonenberg: ping?
<awygle> no, just a fuse
<rqou> wat you actually have a fuse?
<rqou> arrgh why are kicad footprints broken fucking again
<rqou> you always have to muck around with fp-lib-table and sym-lib-table until things work
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<awygle> Rev a had a fuse, Rev b has a protection ic
<rqou> in general i don't bother
* awygle is shocked
<rqou> wait, kicad actually distinguishes pin header and pin sockets? that's kinda neat
<rqou> i usually just did "lol, holes"
<rqou> is bml_khubbard in this channel?
<rqou> huh, kicad's footprints for headers is the opposite of what the pmod spec defines
<rqou> hey awygle, do you happen to know which of kicad's SMA footprints is most common/popular?
<rqou> well, the "no suffix" one is cheapest, so i guess i'll pick that :P
<rqou> quality engineering :P
<awygle> Lol
<rqou> i mean, the sma will be working at <= 100 MHz, so whatever
<rqou> awygle, azonenberg: do you know wtf "Errors occurred creating symbol library" is?
<rqou> dumb question: what's the difference between lqfp and tqfp?
<rqou> other than lqfp for some reason has smaller courtyards
<awygle> I think pitch? Or height
<awygle> I'm not sure it means anything consistent
<rqou> pitch is the same
<rqou> probably height then
<rqou> i don't really care about height
<awygle> Same with **BGA
<cr1901_modern> rqou: It's the height: https://github.com/pcbhdl/pcbhdl/wiki/Package-Dimensions
<awygle> T is usually "thin" for height
<cr1901_modern> Link to relevant standard too
<rqou> afaik that standard costs money
<cr1901_modern> well if you click the link you get a PDF
* awygle quietly adds to archive
<rqou> so, i'm going to be brave and trust a kicad bga footprint
<rqou> wish me luck?
<rqou> oh wtf?
<rqou> apparently that error i got earlier means "i ate your schematic symbol, fuck you"
<rqou> huh, this is actually really bad
<rqou> at any time a kicad lib refactor can just go and ruin your schematics
<rqou> azonenberg why are your oscillator footprints all so bespoke?
<rqou> awygle: how do i calculate the dimensions of the footprint for an exposed pad given the dimensions of the pad?
<azonenberg> rqou: what do you mean about my oscilators?
<azonenberg> awygle / rqou: just thickness
<rqou> azonenberg: your OSCILLATOR_XxY footprints
<azonenberg> yeah what about them
<azonenberg> theres multiple sizes of oscillator
<rqou> they're very bespoke and don't have any silk/fab/etc. layers
<azonenberg> i never use fab layers
<azonenberg> and i think they have markings for pin 1
<azonenberg> but in general most of my designs are high density
<azonenberg> heck, my default 0402 print has no silk either
<rqou> azonenberg: how do i figure out the correct size for an exposed pad without trying to pirate the ipc spec?
<azonenberg> because i expect you to be using it under a bga
<rqou> *the footprint for an exposed pad
<azonenberg> rqou: i go off the chip vendor dimensions
<rqou> no recommended footprint that i can find
<azonenberg> i meant the package dimensional drawing
<azonenberg> if thats all i can get
<rqou> azonenberg: also, what have you been doing the whole day? i didn't see any commits from you :P
<rqou> azonenberg: so pcb pad size exactly the same as package pad size?
<rqou> infineon appnote says do it that way
<rqou> TI has an appnote recommending a SMD center pad rather than NSMB
<rqou> *NSMD
<rqou> hrm, it seem some people definitely expand the pad a little bit
<azonenberg> rqou: i havent pushed everything but i was also doing cleanout in the garage
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<rqou> azonenberg: so does "expanded by 0.05mm from max" sound like a proper size for the exposed pad footprint?
<rqou> azonenberg: what's a good amount of paste coverage for an exposed pad?
<awygle> rqou: the Kicad people prefer slightly larger thermal pad than the one on the chip
<awygle> 50-70% paste
<rqou> yeah, i've done 0.05mm larger each dimension, copied from some random appnote
<rqou> wow, that's very little paste
<awygle> That sounds totally reasonable
<awygle> 70% is the standard
<awygle> Ideally relatively evenly distributed
<awygle> And not directly above thermal vias
<rqou> huh, it turns out that my "eyeballed" paste pattern is actually 52% coverage
<rqou> so good enough :P
<rqou> no thermal vias in this footprint lol
<rqou> if your 240 LE CPLD is dissipating more than 1W you already have a major problem
<rqou> azonenberg: what oscillators do you normally use?
<rqou> the full model number
<rqou> observation: BGAs are smol :P
<rqou> e.g. they're only slightly bigger than the area taken up by right-angle pin headers
<rqou> QFPs are lorge :P
<awygle> Neither of those is necessarily true lol
<rqou> well, i have a qfp144 and a bga256
<rqou> oh wtf the kicad pads are _rounded_
<rqou> i guess that works
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<rqou> awygle: does kicad finally have the ability to save layer colors yet?
<awygle> *shrug* no idea
<awygle> I didn't change the defaults
<rqou> the defaults are almost unusable imo
<awygle> You're not necessarily wrong lol
<awygle> Good luck with PCBs, fireworks are over, nobody's building furniture upstairs, I'm going to bed
<ZombieChicken> Has Lattice made any comments about the open source toolchain for (some of) their FPGAs?
<rqou> yes, but the symbiflow team won't share them
<ZombieChicken> but apparently nothing like like a C&D?
<rqou> no
<ZombieChicken> That's good to know
<rqou> ugh, all of these color palette pickers seem to suck for some reason
<ZombieChicken> What do you need one for?
<rqou> pcb layer colors :P
<ZombieChicken> Just do it all in Red, Blue, and Yellow
<ZombieChicken> iirc, that's enough for a map, so it should be enough for a PCB
<ZombieChicken> Or did you need 4 for a map?
<azonenberg> You need four
<ZombieChicken> R, G, B, & Y then
<rqou> i'm basically doing that
<rqou> not quite exactly like that though
<rqou> since there's a _lot_ of layers in a pcb
<rqou> i'm currently doing red/purple/orange/blue for cu layers
<rqou> yes, heretic i know :P
<ZombieChicken> Purple is a nice color
<ZombieChicken> think it clashes with orange, though
<rqou> red/blue are the heretical colors
<rqou> yes, i deliberately want color clashes
<rqou> so i can tell what is supposed to be on what layer
<ZombieChicken> sounds like me and my hot pink duct tape
<rqou> anyways, red/blue for top/bottom is EAGLE default colors
<rqou> red/green are kicad default colors
<rqou> but i'm used to the eagle way
<ZombieChicken> How are you liking kicad?
<rqou> it's okay
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<openfpga-github> [openfpga] cr1901 opened pull request #124: gpcosim VPI module and iverilog tests now compile on Windows (MinGW64). (master...vpi-win) https://git.io/fbpXc
<cr1901_modern> Took me long enough
<rqou> somebody sure wanted to shave some yaks today :P
<cr1901_modern> Maybe, but seeing so many entries on my Todoist irritates me, so I'm trying to get old ones done before doing new ones
<cr1901_modern> s/doing/making/
<cr1901_modern> Oh and xptools currently needs 3 lines added
<rqou> yeah i hate how everything is in separate repos
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<rqou> anyways, azonenberg now just needs to actually make gpcosim useful :P
<cr1901_modern> azonenberg: After you take a look and approve, could you update the submodule commit?
<rqou> whelp, initial board size estimate is 10 inches by 3 inches
<rqou> that's... way too big
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<rqou> hmm, the problem is board edge space, so i should be able to shrink this by cleverly reshaping the board
<rqou> hrm
<rqou> new dimensions are ~5x5 in
<rqou> azonenberg: ping?
<cr1901_modern> That's still $75 at OSHpark ._.
<cr1901_modern> actually no, $125
* cr1901_modern can't multiply
<rqou> 4-layer
<cr1901_modern> 250 then
<cr1901_modern> wth are you making?
<rqou> so, anybody have good ideas how to make this smaller?
<rqou> azonenberg?
<rqou> a huge problem is that PMODs must be on the edge of the board
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<rqou> final size 5.3x4.1 in
<rqou> hrm
<rqou> i guess i can afford that
<rqou> PMOD is a huge pain in the ass
<rqou> since it has pretty precise mechanical specs
<cyrozap> rqou: 1. Replace the giant TQFP parts with smaller BGA versions. 2. Move the PMOD connections to a cheaper, 2-layer daughterboard connected with an FFC or something.
<rqou> but FFCs are a pain
<rqou> also, one of those TQFPs cannot be switched
<cyrozap> Also I see you're using an entirely-SMD micro-USB connector. Bold move...
<rqou> i've had good luck with it?
<rqou> i've used it many times
<cyrozap> I like to be able to dangle devices by the cable without any fear of ripping off the connector. Not that I'd actually _do_ that, but I've had so many bad experiences with products that use those SMD connectors that I've decided to never use them in anything I design. :P
<cyrozap> *cough* DIGILENT *cough*
<Prf_Jakob> rqou, cyrozap: Use a SODIMM connector?
<rqou> wrong thickness of pcb for oshpark
<Prf_Jakob> Ugh right
<cyrozap> rqou: You could also use B2B connectors and skip the cable. Give your PCB some wings ;)
<rqou> lol
<rqou> which company's marketing-speak was "wings" again?
<cr1901_modern> papilio
<cyrozap> Shields, capes, wings, hats...
<rqou> it's so dumb
<cyrozap> When is anybody going to make a board that uses skirts/dresses/bonnets/bows?
<cyrozap> Call it "board-chan"
<rqou> somebody already used bonnet
<rqou> personally i'd prefer if we stopped using these silly names that are only cute the first time
<cyrozap> Ah, looks like it's Adafruit: https://www.adafruit.com/?q=bonnet
<cyrozap> "pantsu"
<rqou> but whitequark was claiming that people use them because it helps newbies not be intimidated or something
<cyrozap> Go full-anime
* cyrozap needs to sleep
<Prf_Jakob> rqou: PCIe connectors
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<awygle> rqou: get it at seeed or someplace with a different price structure than osh
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<azonenberg> cr1901_modern: around?
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<azonenberg> cr1901_modern: you have the right fix, but in the wrong place
<azonenberg> i won't be accepting your xptools patch
<azonenberg> because the namespace collision is with an enum defined in logtools
<azonenberg> If you put the same thing in log.h i'll accept it
<cr1901_modern> azonenberg: Ack, I'll fix it in an hour or so
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<rqou> wait
<rqou> i swear i fixed this problem before
<rqou> this also undefs ERROR
<cr1901_modern> Of course it does...
<rqou> also, azonenberg: have we decided yet what we want to do about the VPI headers in a post-oracle-vs-google world?
<rqou> cr1901_modern: so my undef is not sufficient?
<azonenberg> i'll let you two figure this out, but either way that PR is not getting merged
<azonenberg> as it seems to be in the wrong place
<rqou> azonenberg: and VPI in a post-oracle-vs-google world?
<cr1901_modern> rqou: I would say no it's not sufficient
* cr1901_modern makes a test
<cr1901_modern> rqou: __WINPTHREADS_VERSION is defined on my machine
<cr1901_modern> So move the #undef error out of that #if-block and into a new "#if defined(__MINGW32__)"-block or move the #if !defined(__WINPTHREADS_VERSION) test _into_ the existing #if-block
<openfpga-bot> [jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fbjej
<openfpga-bot> jtaghal-apps/master c169454 Andrew Zonenberg: jtagclient: Changed default verbosity for device-count message
<azonenberg> LOl
<azonenberg> LOL*
<azonenberg> the coresight device ID for a cortex-a9
<azonenberg> is 0xC09
<azonenberg> i wonder why not 0xCA9?
<jn__> that's the model number register value too
<jn__> curiously you can read this as ARM1209 :)
<openfpga-github> [logtools] cr1901 opened pull request #5: Update log.h (master...patch-1) https://git.io/fbjJk
<cr1901_modern> And hopefully after this, the Windoze build will work for a few more weeks :)
<openfpga-github> [logtools] azonenberg pushed 1 new commit to master: https://git.io/fbjIr
<openfpga-github> logtools/master 842945c Andrew D. Zonenberg: log: fixed bugs where some class constructors didn't get LogTrace()'d correctly
<openfpga-github> [logtools] azonenberg closed pull request #5: Update log.h (master...patch-1) https://git.io/fbjJk
<openfpga-bot> [jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/fbjI9
<openfpga-bot> jtaghal-cmake/master 5a03697 Andrew D. Zonenberg: Updated to latest logtools
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<openfpga-bot> [jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fbjnI
<openfpga-bot> jtaghal/master 50ad5ef Andrew D. Zonenberg: Lots of refactoring of ARM CoreSight classes
<openfpga-bot> [jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/fbjnq
<openfpga-bot> jtaghal-cmake/master f76a193 Andrew D. Zonenberg: Updated to latest jtaghal
<cr1901_modern> azonenberg: Does this look okay to accept? https://github.com/azonenberg/openfpga/pull/124
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