<mithro> Anyone know why icebox_vlog would be trying to assign zero to a reg value?
<mithro> iceram_bit.v:1889: error: reg n26; cannot be driven by primitives or continuous assignment.
<mithro> assign n26 = 1'b0; when reg n26 = 0;
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<mithro> It seems to be coming from "const_assigns" ....
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<rqou> azonenberg, awygle: ping?
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<rqou> or anybody in this channel who is good at teh PCBz
<rqou> can i get a design review? https://github.com/rqou/project-chibi-dev-board
<rqou> this is close-to-final unless major issues come up
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<cr1901_modern> azonenberg: Could you sign off on this? https://github.com/azonenberg/openfpga/pull/124
* cr1901_modern forgot he had commit access to this repo, but... asking just to be polite
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<q3k> i made a verilog/rsic-v challenge for wctf2018; https://hardflag.q3k.org/
<q3k> if anyone feels like hacking
<q3k> marcan: ^
<cr1901_modern> q3k: Could you check your privmsgs when you get the chance?
<q3k> yeah, sorry, just have been traveling a lot recently again
<cr1901_modern> no worries, it's not like I've been doing a great job either lol
<cr1901_modern> q3k: (And you have a good reason. I'm just _really_ bad at multiplexing even when I'm at the computer.)
<q3k> well it's not like im the paragon of responsiveness, too :P
<rqou> offtopic: i'm surprised byuu doesn't like Rust with all of the things that they want out of C++
<rqou> although having type-level integers would be really really helpful
<cr1901_modern> Short version (I don't want to talk about it): byuu is not fond of Mozilla period.
<rqou> i mean, i'm not either
<rqou> mozilla seems to have totally lost their way, but the Rust team seems reasonably unaffected for now
<rqou> although tbh i feel the entire "web infosec people" just seem to love doing user-hostile things
<cr1901_modern> In any case, you'd be the 50th person to suggest Rust to him :). He's relaxed a bit, but suggesting it used to be a good way to get him to rant.
<rqou> idk, byuu seems to have a really unusual coding style
<rqou> but then i guess i do to, and my style fits Rust better
<sorear> i'm a little bit surprised they haven't set up a legal entity to own the trademarks yet
<rqou> awygle do you have time now? i see you on birbsite
<awygle> lol stalker
<awygle> yeah sure
<awygle> I just got home
<rqou> hey, blame the Algorithm(TM)
* awygle loves bruce willis movies
<rqou> heh
<rqou> i don't really do movies
<awygle> rqou: can you toss up a PDF and some images? i don't have kicad on this pc
<rqou> ok, sec
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<awygle> i just got back from a movie which sadly lacked bruce willis (Ant Man and the Wasp)
<rqou> lol you actually do movies?
<awygle> it's a thing my dad and i do together
<awygle> otherwise i wouldn't pay for a theater seat
<awygle> lol the scientific name for the black rat is "rattus rattus"
<awygle> poor little guy
<awygle> mk, i'll take a look, please wait warmly
<cr1901_modern> awygle: Ahhh yes I go and see that tomorrow
<rqou> awygle: "first board with [m]ore than two layers+BGA, be gentle" :P :P :P
<cr1901_modern> Unfortunately, my taste in movies is considered suspect by others *cough* zino *cough* (I _liked_ BvS: Dawn of Justice)
<awygle> rqou: (and actually cr1901_modern if you don't mind): while i'm looking at this, are there any other things along the lines of "how do i do decoupling good" that you feel or felt unsure of, or that were never explained well?
<rqou> i mean, i never learned PCB design "for real" even at $FANCY_SCHOOL
<rqou> my PCB skills are basically entirely self-taught based on looking things up on the interwebs and just building boards
<rqou> (and then we wonder why we can't find talent, blah blah blah <insert usual drama here>)
<cr1901_modern> Put two caps, for each IC, one w/ 10s more capacitance to cancel out the inductive effects of the other. Nothing you don't already know :P.
<cr1901_modern> 10 times*
<awygle> rqou: sure, and there are a lot of people like that. i'm just wondering what you feel are the holes in that transfer of knowledge.
<awygle> thinking about writing some blog posts maybe
<rqou> i'm in general not super good at decoupling or analog/rf
<rqou> since i'm mostly a "digital" guy
<rqou> despite having my extra-class ham radio license lol
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<awygle> hm, don't install both the 3-pins and the SMAs for clock
<awygle> depending on clock rate i guess
<rqou> i specifically want the 3-pin to allow you to cheat and not care
<rqou> about signal integrity
<rqou> i'm hoping that it won't degrade a "real" clock signal too much
<awygle> sure, but if you _do_ care, the pin will cause a stub
<awygle> the hole is probably fine, but the long pin may not be
<rqou> what if i just install only one or the other?
<awygle> that should be fine yeah
<awygle> why do you have a jumper from ground to ground?
<rqou> for clipping scope probes
<rqou> yeah yeah i know, should get the springs
<rqou> azonenberg uses special thingies specifically designed for you to clip probes, but i find that a pin header is cheaper :P
<awygle> yeah i'm with you there :p
<rqou> ugh digikey changed their favicon and now i'm confused whenever i look at my browser tabs
<awygle> rqou: this looks fine
<awygle> i'm a little bit uncomfortable with the 40 MHz clock routing
<awygle> specifically in the bottom left quadrant where it does a few jumps back and forth from top to bottom
<rqou> yeah, i was trying to avoid the gap in the power plane
<awygle> because the reference plane change isn't handled _totally_ optimally
<awygle> (you have a 3V3 to GND cap nearby but not like, _right_ nearby)
<awygle> also how much current do those oscillators drive? they might not expect that much loading
<awygle> but again, both of those things are probably fine, i'm just nitpicking
<awygle> (also you still didn't widen that 5V trace to the plane :p)
<rqou> lol oops
<rqou> afaik these are supposed to be "lvcmos" output drivers on the oscillators
<rqou> so probably fine?
<awygle> i'd personally throw on 3 fiducials if i were you but if you're never gonna get this assembled out of house, nbd
<rqou> oh yeah fiducials are a thing
<rqou> meh, probably won't bother
<awygle> oh and definitely include your mounting holes in your paste layer. it makes alignment waaaaay easier.
<rqou> how do i change that in kicad?
<awygle> check f.paste and b.paste in the pad properties
<awygle> under technical layers
<rqou> ah ok
<rqou> and now the 3d viewer is like "oh, you want solder paste over this hole?"
<awygle> well yes there's that lol
<awygle> your mask expansion is such that you have no webbing on the upper left quadrant qfp
<rqou> yeah
<awygle> idk if it would even be fabbed though, they might just clip it
<rqou> yeah, i didn't realize it, but that footprint _sucks_ to use
<rqou> who the heck makes QFPs with exposed pads?
<awygle> yeah course, fine pitch qfp with a thermal pad
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<awygle> they combined my and azonenberg's nightmares
<rqou> cheap though, 90 cents each on digikey
<awygle> rqou: RF people do sometimes which is weird. low inductance grounding... and then hella lead inductance.
<rqou> oh, and the exposed pad is mandatory
<rqou> it's the _only_ gnd connection on the chip
<rqou> to maximize IOs i guess
<azonenberg> awygle: yeah i dont get it
<awygle> that's not that uncommon these days
<azonenberg> why not go bga?
<awygle> i mean QFN is the ideal rf package in a lot of ways, sadly
<awygle> BGA isn't too bad either
<azonenberg> *wirebonded* qfn? :p
<awygle> idk, lot of machine capacity
<azonenberg> can you say L?
<awygle> azonenberg: lol yeah ok
<awygle> fair point
<azonenberg> IMO the ideal RF package is flip chip WLCSP
<rqou> all of these packages are wirebonded
<rqou> even the bga
<awygle> aka "non wire bonded QFN" :p
<awygle> anyway i'm done rqou. i didn't run azonenberg's checklist, so maybe do that, but it looks pretty decent to me overall.
<buhman> WLCSP looks like a ~regular BGA; why is it special?
<azonenberg> buhman: there's no fan-out
<azonenberg> a "normal" BGA you wirebond the die to a FR4 substrate then put solder balls on that
<azonenberg> a flip-chip BGA you solder-bump the die to a FR4 substrate then put balls on that
<awygle> there are lots of things labeled "wlcsp", too. it just means "the package is not much bigger than the die".
<rqou> uh, not necessarily
<azonenberg> but in both cases the pacakge is much bigger than the die to allow for saner PCB design rules
<rqou> there are some wlcsps with polyimide layers
<azonenberg> whereas with a WLCSP, you basically put solder balls on top of the wafer
<azonenberg> then dice it up
<awygle> c.f. TI's XSON nonsense
<azonenberg> and that's your packaged chip
<rqou> azonenberg: what's polyimide "advanced packaging" count as then?
<azonenberg> awygle: in my taxonomy, a WLCSP means you put down a polyimide layer over the wafer
<azonenberg> solderbump it
<azonenberg> then dice it
<azonenberg> and call it done
<azonenberg> i.e. no package, no fanout
<rqou> but there are WLCSPs that don't need the polyimide layers
<azonenberg> at most, a thin layer of epoxy or black paint on the back of the die to keep light out
<awygle> azonenberg: i wish we lived in a world where things were as clean as they are in your ~religion~ taxonomy :p
<azonenberg> there are plenty of chip scale packages that are other designs
<rqou> azonenberg: don't like "shy" RasPis? :P :P
<azonenberg> but WLCSP implies wafer-level packaging
<azonenberg> So you cant have any fanout because, well, the package is built on top of the wafer and then diced
<rqou> also, azonenberg, now that you're here, can you please take a look at my board?
<buhman> where's this board?
<azonenberg> in a few, have some higher priority stuff to do
<rqou> so, i'm about to order "the cheapest LEDs i can get" again
<rqou> i wonder if i will end up blinding myself?
<rqou> i did the "¯\_(ツ)_/¯ 330 ohm" thing
<awygle> you definitely will go blind and should do the math
<rqou> but the math is hard :P
<awygle> so is LASIK
<rqou> lol
<awygle> (idk if that's true or even relevant but it felt appropriately snarky)
<rqou> btw another recent birbsite thread that i found pretty funny was Fiora asking for "halp, i want a calculator for presumably LEDs and stuff but don't want a complicated ECAD tool"
<awygle> there's a piano someplace outside my apartment but every time i get up to go look for it it stops playing
<rqou> actually, thinking about it more, why is engineering so inaccessible?
<rqou> it shouldn't be this way
<awygle> i agree wholeheartedly
<awygle> this is why i hate when people are like "lol circuitmaker" or whatever
<awygle> "lol arduino"
<awygle> those tools serve a crucial role
<awygle> also why i have huge respect for people like e.g. manishearth, who work on docs and onboarding and all that good stuff for inherently-complex projects like rust
<rqou> i just added like $50 worth of connectors
<awygle> lol yuuuup
<awygle> and those are mostly cheap connectors too, except the SMAs
<rqou> yeah
<rqou> these are just generic right-angle pin headers
<awygle> idk why. the charitable answer is "material cost" but idk if that's actually it.
<rqou> wtf why do dip switches have a "washable yes/no" selection?
<awygle> depends what you need to dip them in
<rqou> hey um, dip switches are standardized dimensions, right?
<rqou> ie "DIP sized?"
* awygle shrugs
<rqou> what's the exact difference between "frequency stability" and "frequency tolerance" on a crystal?
<awygle> frequency tolerance is "difference from ideal at 25C"
<awygle> frequency stability is is "difference from 25C over operating temperature range", usually
<rqou> hmm, so i assume for the ft232h i need <= 30 ppm for both
<awygle> sometimes you get non-temperature stability values like "over 10 years" or whatever
<awygle> temp is unlikely to be a serious issue for you since they're probably specced at least 0/70 and you'll be in like... 20/30
<rqou> whee, this board is going to cost me half a grand including parts
* awygle reiterates low-cost fab options
<rqou> well, it's $350 in components
<awygle> yeah that seems high
<awygle> connectors?
<awygle> or CPLDs?
<rqou> $50 is connectors
<rqou> a bit over $200 for CPLDs
<awygle> ah ok
<awygle> well *shrug* i guess
<rqou> and then everything else like LEDs and crystals and shit
<rqou> also any passives i might need (but i think i have usable ones in my parts bin that predate the current shortage)
<rqou> azonenberg: willing to say how much your Coolrunner-II board cost?
<azonenberg> rqou: cant begin to guess
<azonenberg> it was like 4 years ago
<rqou> is $500 for my board about right?
<azonenberg> bare pcb or parts too?
<azonenberg> does that include a stencil?
<rqou> pcb+parts
<azonenberg> my CPLDs were way cheaper than yours
<rqou> hmm
<rqou> 5m40z is 90 cents
<azonenberg> the 2c256 is under $20
<rqou> but the 5m2210z is like $20
<azonenberg> $19 or so
<azonenberg> the 32a was, at the time, about a buck
<azonenberg> then 64 and 128 plus one more for the crossbar
<azonenberg> so maybe $50 in cpld total
<rqou> hmm so this should be about the samr order of magnitude
<azonenberg> i also had pmod only, no sma's
<rqou> oh, this is for 3x boards
<azonenberg> good smas are $5-10 eachj
<azonenberg> ... oh
<azonenberg> that souds totally reasonable then
<rqou> i didn't include the SMAs
<awygle> Oh if that's 3x then yeah
<rqou> yeah, it doesn't make much sense to spend so much effort and make 1x board, does it? :P
<rqou> even azonenberg made 3x
<awygle> I usually build 2. But I'm usually just building for me.
<azonenberg> i normally do 1 of most of my designs
<azonenberg> i do 3 if i'm using several, like my jtag dongle (i think the only board i've ever done >1 prod run of at oshpark)
<azonenberg> Or, in this case, if i want boards to sell/give to other people
<azonenberg> since i gave one to you and one to diamondman
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<rqou> man, fuck "Current market demand for these product types have resulted in fluctuating and extending lead times. Lead times may differ."
<azonenberg> trying to buy capacitors? :p
<rqou> yeah
<rqou> i have some on hand but not all
<rqou> whee, hirose didn't do anything dumb and their micro-b footprint is compatible with their micro-ab footprint
<rqou> azonenberg: why are NP0/C0G capacitors so much more expensive?
<azonenberg> Not entirely sure, probably tougher manufacturing tolerances or something? idk
<azonenberg> in general i got X[5|7]R for decoupling
<azonenberg> Y*V has terrible performance under bias
<rqou> yeah, i know
<rqou> i get NP0/C0G for crystal load caps only
<azonenberg> NP0/C0G is good for RF or when you need precision values but for decoupling IDGAF about the exact value, i just want decent C/V
<rqou> at least for now
<azonenberg> i generally prefer to use oscillators to crystals
<azonenberg> infinitesimal increase in cost, i can feed directly to an FPGA or clock buffer
<azonenberg> less passives to place, less noise sensitive layout
<rqou> hrm, i'm seeing ~$2 for an oscillator, 40 cents for a crystal
<rqou> quite significant for higher volumes
<azonenberg> infinitesimal when you have a $300 FPGA on the board :p
<azonenberg> I dont do cost optimized high volume designs
<azonenberg> i mostly do one-offs that have high BOM cost in capital components and where system cost is dominated by PCB NRE and engineering time
<rqou> ouch, once i put in all the "misc" the final parts order is $380
<azonenberg> Which is why i have so much focus on conservative "right first time" design practices rather than pushing limits of how cheap i can go, how few decoupling caps i can have, etc
<rqou> my wallet :(
* azonenberg looks over at $1200 digikey cart pending for LATENTRED
<rqou> anyways, i'm placing the parts order now even though i totally don't have to
<azonenberg> that's for one unit, not counting PCBs, and that's only the major ICs for the brain card
<rqou> but it's unlikely to change, unlike last-minute PCB tweaks
<azonenberg> i dont think i have the buffers for the backplane either
<rqou> btw azonenberg, do you have a chance to look at my design?
<azonenberg> i looked at the screenshots you tweeted
<azonenberg> didnt do a full design review
<azonenberg> thats what the checklist is for
<rqou> i uploaded the kicad file to github
<azonenberg> nice, but i dont have time to do a full review
<rqou> my only concern is that i have funky-looking internal planes because of where vias get positioned
<cr1901_modern> azonenberg: Potential sidegig opportunity ;)
<rqou> also the 1.8v plane gets all cut up by the gnd vias in the BGA
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<rqou> azonenberg: can you comment on via placement vs planes in this part of the board: https://photos.app.goo.gl/MiiwRGRGcwGeyUHd7
<rqou> is this ok?
<awygle> It's not great. It should be OK if you don't need much current.
<awygle> And assuming decoupling of course
<rqou> current isn't too high
<rqou> how can i do better?
<awygle> Hard to see how much latitude you have but if you can swap which side you break out on for some of those balls, you might get the 1v8s closer together
<awygle> Otherwise... Do the remnants of that plane end up thicker than the biggest trace you can fit? If not, run traces instead maybe
<awygle> Tough to do a *lot* better on 4l
<awygle> Maybe change the 3v3 breakouts too so you can go around the outside of the dense section
<awygle> That make sense?
<rqou> but that doesn't really help the gnd vias getting in the way?
<rqou> ooh i think i see
<rqou> hrm, that would be annoying
<rqou> is this "good enough?"
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<awygle> Yeah it's probably fine
<awygle> Almost definitely fine in fact
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<rqou> so, who wants to suggest which chibi should go on the pcb as art? :P
<rqou> probably kanna?
<cr1901_modern> The hell is tha- oh, that dragonmaid show
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<rqou> random: i love bitmap2component
<rqou> so much better than the crappy eagle scripts
<rqou> azonenberg_work: question: how many easter eggs do you like to put on your boards?
<azonenberg> rqou: as a general rule, i just use the Long Thing as a "signature"
<rqou> what is that thing btw?
<azonenberg> It's a bit of family lore that goes back about 15 years, lol
<azonenberg> We had an L-shaped bunk bed with my brothers on a double mattress on the bottom and me on top in a single
<azonenberg> No ladder, you had to stand on the bottom bunk to get to the top
<azonenberg> one of them was on the bottom bunk as i climbed up to the top
<azonenberg> I was a skinny teenager and from his shallow-angled viewpoint i looked even skinnier
<azonenberg> made some comment about me being "so long it made him sick"
<azonenberg> so of course my brothers took that quote and ran with it
<azonenberg> and invented this species of creatures called "long things" that were 7-dimensional monsters that could ooze through a hole the size of a quarter
<rqou> wtf
<rqou> you guys are all a bunch of nerds
<azonenberg> had eye stalks (that they called eyelids, but they were really on stalks)
<azonenberg> left radioactive slime trails of "long juice" behind them kinda like alien slugs
<rqou> i don't have a super consistent signature, but recently i've taken to hiding nyan cats under QFPs
<azonenberg> they like to ooze slowly down pipes too, and sometimes get jobs as plumbers cleaning out clogged pipes from the inside
<azonenberg> Long juice also is an excellent lubricant so they often work as mechanics too
<azonenberg> Anyway, many years later i had ally draw a long thing off my brother's description
<azonenberg> the resulting image started out as a full color drawing but she traced it to line art and i made a kicad symbol
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<rqou> also, pcb finishing touches like final signoff and silkscreen take _forever_
<azonenberg> Yes
<rqou> should just be like your client and not check :P
<azonenberg> Lol
<azonenberg> that's how you get a bunch of respins :p
<rqou> also, idk about you, but every time i plot final gerbers and inspect them, i always find some OCD things to tweak
<azonenberg> me too
<azonenberg> btw
<azonenberg> is a long thing oozing slowly down the pipes
<azonenberg> or in this case, oozing out of a pipe
<rqou> ugh i keep forgetting gerbv (my preferred gerber checker) isn't accelerated
<azonenberg> yeah i use gerbv too
<azonenberg> it's... not fast
<azonenberg> on large designs
<azonenberg> i really should check gerbview out at some point
<rqou> on a 4k screen
<azonenberg> yeah same here
<azonenberg> big design, 4k screen, not fast
<rqou> i've found the kicad gerber viewer too cluttered
<rqou> iirc i've been using gerbv since SFE recommended it over a decade ago
<rqou> apparently they (used to at least) used it because it specifically had no features
<rqou> azonenberg: do you put layer numbers on your boards?
<rqou> for testing?
<azonenberg> I normally put them on larger designs, yes
<rqou> to keep the fab honest? :P
<azonenberg> good for sanity checking as well as to make sure i have the layers in the right order when i send to fab, render them, etc
<azonenberg> so far i've never caught a reordering
<rqou> apparently people on the interwebs have seen it before
<azonenberg> I should probably get some sleep though
<rqou> especially when boards are 10+ layers
<azonenberg> Sheetrock comes tomorrow at an unknown time
<azonenberg> so i have to be at the house all day :p
<azonenberg> Which means getting up early so i can get there well before any plausible delivery
<rqou> btw, random question
<rqou> i wonder how many humans at oshpark actually look at designs
<rqou> do you know anything about this?
<azonenberg> Nope
<rqou> iirc pdp7 remembers you
<rqou> apparently he said that you submit boards of relatively high complexity compared to others
<azonenberg> Lol
<azonenberg> cant say i am surprised
<azonenberg> i do a lot of bgas, fpgas, ethernet, etc
<azonenberg> when you mostly see arduino clones etc stuff of this level is relatively rare
<rqou> i wonder what this project chibi test board would be on the complexity scale?
<azonenberg> i know a few other people that do high end stuff on oshpark
<azonenberg> like harmoninstruments
<azonenberg> but its not a long list
<rqou> shit
<rqou> azonenberg: what's the normal pad diameter for 256-ball BGAs?
<rqou> the kicad footprint i used without looking has 0.4 mm
<rqou> the chip itself is nominal 0.6 mm
<azonenberg> it depends on the ball diameter
<rqou> wait
<azonenberg> not all bgas of the same pitch have the same ball size
<rqou> wow, altera's package drawing sucks
<rqou> it has a dimension labeled "b" that appears to be the diameter of the ball
<rqou> which is nominal 0.6 mm
<rqou> so the pad is smaller?
<azonenberg> You want 450 +/- 50 um pads
<azonenberg> So 400 um is on the low end of the acceptable tolerance
<rqou> why 450?
<azonenberg> This is a TI wiki page mirroring a table from IPC-7351A
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<rqou> xilinx has 0.4 mm for their BGAs
<azonenberg> The FTG256 package is 0.5mm ball diameter
<azonenberg> So 0.4mm pad makes sense for those
<rqou> wait, so altera's has larger balls, or what?
<azonenberg> Your package has larger balls on the same pitch, yes
<azonenberg> So you want a slightly larger land diameter ideally
<rqou> hrm
<azonenberg> 400um will still work, just wont be quite as solid of a joint
<azonenberg> it's exactly the low side of the tolerance range
<azonenberg> so if you overetch the pad, you might be out of spec
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<rqou> wait a sec, xilinx FB/FT is not the same as FF/FG/FH/FL/RB/RF?
<azonenberg> I think its package size mostly
<azonenberg> FG676 is 600um
<rqou> apparently the balls are different sizes
<azonenberg> FF1156 is 600
<azonenberg> FB484 is 600
<rqou> why are you measuring everything in um btw?
<azonenberg> i dont like mils, and fractional mm is an annoying thing to type
<azonenberg> especially when most dimensions in a PCB are sub-mm
<rqou> be kicad and measure in nm? :P
<azonenberg> I use um to measure trace width/space, stackup, etc
<azonenberg> and mm for larger dimensions like package size
<rqou> so if i just don't put paste for the altera bgas and do flux-only, then 400um should work? :P
<azonenberg> if anything, with underside pads i'd say you might want a touch more solder
* rqou doesn't want to have to mess around with the layout a whole bunch
<azonenberg> but hard to be sure
<azonenberg> it should work fine
<rqou> also, the xilinx pcb docs are way better than altera's
<azonenberg> anyway it looks like basically all large xilinx 1mm packages are 600um balls, ft256 is 500, most of the 0.8mm packages are 450 or so
<azonenberg> most of the 0.5mm are 300um ball dia
<rqou> why does altera have larger solder balls? what does that gain them?
<azonenberg> ft256 is kinda the odd man out using smaller balls on 1mm pitch than the others
<azonenberg> More standoff height, slightly more room to flex for thermal expansion
<rqou> hrm
<rqou> but neither of these matter for these parts
<azonenberg> with larger pads, a sturdier attachment
<azonenberg> dont know, just thinking out loud
<rqou> heh
<rqou> there's an altera appnote about that btw
<azonenberg> but basically, with xilinx it seems like any given (pitch, ball count) has the same ball diameter
<azonenberg> so footprint compatible packages are the same
<rqou> apparently the huge stratix 10s have a weird recommended footprint
<azonenberg> but as you change ball count or pitch they may vary diameter
<rqou> the corner balls are SMD on an otherwise NSMD footprint
<azonenberg> o_O
<rqou> apparently for mechanical reasons
<azonenberg> You remind me i want to try making an octagonal 0402 passive footprint
<rqou> because the corners are more susceptible to damage
<azonenberg> To fit between 1mm pitch bga balls
<azonenberg> i know folks who have used this to great success
<rqou> i'm currently just using kicad's rounded rectangle ones
<rqou> (sorry, not your bespoke ones)
<rqou> i'm actually trying to do a "use kicad libs as much as possible" design
<azonenberg> meanwhile i go with "what i know works and have personally tested, so low risk" design as much as possible
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<rqou> hmm yeah the kicad package really is designed for larger balls
<azonenberg> because i dont want to trust $1k+ of components to a footprint i havent thoroughly vetted
<rqou> *smaller
<azonenberg> and if i have vetted it, i did as much work as doing it myself :p
<rqou> azonenberg: so, final verdict: what do you think i should do about my bga pads?
<rqou> leave it?
<azonenberg> tweak/
<azonenberg> ?
<rqou> hrm
<rqou> i guess i can do that
<rqou> 0.5mm?
<rqou> will be "fun" to see how many traces need to be rerouted after that
<rqou> huh, apparently no major issues
<rqou> flushed out some bugs that were there before
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<rqou> pie__: which chibi should go on the project chibi test board? :P
<rqou> currently it's kanna kamui
<pie__> i'unno. i guess.
<pie__> (wicked.)
<rqou> alright, it's getting ordered
<rqou> pray for no bugs?
<rqou> or at least no showstoppers
<pie__> rquoli rquoli dont screw up the dragon loli
<pie__> :p
<pie__> rqou, kanna will just eat all the bugs
<rqou> lolol
<pie__> thats gotta be a pretty good good luck charm now that i think about it :P
<pie__> :D
<pie__> nyan accelerator
<pie__> nyanccelerator
<rqou> nyan processing :P
<pie__> nyanccessing
<pie__> /o/
<pie__> ganyway, good [time of day].
* pie__ runs off to $ERRANDS
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<awygle> that looks cool
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<felix_> thx :)
<felix_> https://github.com/felixheld/AXIOM-photonSDI-hw are the design files and http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw.pdf is a recent-ish pdf export of the schematics
<felix_> not completely finished yet, but not that far away from that any more
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<awygle> Oh interesting, I just assumed that was an m.2 connector
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<shapr> speaking of which, I need an m.2 ssd mounting screw
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<azonenberg_work> welp i just found a bug in my arm dap code
<azonenberg_work> it doesnt handle multi-device chains properly because it does low level chain twiddling in a few spots
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<openfpga-bot> [jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fNJsm
<openfpga-bot> jtaghal/master a130048 Andrew Zonenberg: Fixed lots of spots in ARMDebugPort that assumed we had a single device in the scan chain. New code is inefficient but functional
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<azonenberg_work> fixed a bunch more multi-TAP bugs, this is what i get when i connect to a zynq
<azonenberg_work> now to figure out why the heck i cant actually read memory over ahb
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<cyrozap> <rqou> $50 is connectors
<cyrozap> rqou: Are you not buying the connectors from AliExpress?
<rqou> I've also done that
<rqou> they're objectively worse
<cyrozap> They're 2-row 0.1" right-angle headers, right? That seems like it would be pretty hard to mess up...
<rqou> i bought the cheapest 0.1" pin strips a while back and they don't solder as reliability
<rqou> i still use them for quick hacks though
<awygle> mine melt
<awygle> almost immediately
<awygle> the pin melts away from the plastic
<awygle> oh also remember all my complaints about lead-free soldering? turns out the solder i bought was not sac-305
<cyrozap> rqou: How did you measure "solder reliability"? If something isn't soldering for me, I usually just apply more heat/flux depending on the situation.
<awygle> (despite the clear labeling _saying_ it's sac-305)
<rqou> how did you find this out?
<awygle> by using actual sac-305
<awygle> (borrowed from a friend)
<awygle> actually what first tipped me off is that the sticker says "rosin core" and there was no visible flux
<rqou> cyrozap: mostly qualitative assessment of how much heating i needed before the solder would properly wet the pin header, compared to the other pin headers that i acquire from Fry's
<qu1j0t3> awygle: Yeah, mine melt too (PVC?) -- but my iron is likely very hot (not temp controlled)
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<awygle> ugh. that feeling when your code _almost_ works but also is _almost_ too complex to safely modify and you have to decide whether to refactor or get to functional first.
<awygle> qu1j0t3: yeah i think mine just suck, my iron is supposed to be decent at least
<azonenberg_work> awygle: so you like *actual* sac305 with *actual* flux? :p
<awygle> azonenberg_work: still worse than 63/37 but better than the fake stuff
* azonenberg_work actually prefers sac
<azonenberg_work> it seems to perform better for 2 side reflow
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<azonenberg_work> and the math backs it up, higher surface tension forces = more retention of bottom-side parts
<awygle> I don't like the squnchy phase of non-eutectic solders
<rqou> azonenberg_work: ping? can you disable OTR?
<ZombieChicken> Quick question: Anyone know of a Warren Abstract Machine implemented in an FPGA? it's supposed to be doable (in fact, I think the WAM was designed for it), but a quick Google/DDG doesn't seem to show up anything
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<qu1j0t3> ZombieChicken: I doubt it was. It predates the existence of FPGAs slightly, let alone widely available ones
<qu1j0t3> ZombieChicken: (& the preoccupation of CS then was conventional CPUs ... not even RISC)
<ZombieChicken> qu1j0t3: First line of "An Abstract Prolog Instruction Set" by David H. D. Warren starts with "This repost describes an abstract Prolog instruction set suitable for software, firmware, or hardware implementation"
<qu1j0t3> i wonder what he means.
<ZombieChicken> The question is if it's been done in an FPGA
<qu1j0t3> he must have meant a custom CPU/ASIC then
<ZombieChicken> and, unless I'm mistaken, you should be able to implement (or at least closely implement) an ASIC in an FPGA
<qu1j0t3> ZombieChicken: I assume you already asked in #prolog? specifically ttmrichter?
<ZombieChicken> qu1j0t3: I asked, but it's a bad time of day for that kind of thing
<ZombieChicken> I thought 'maybe someone in #openfpga might know something'
<qu1j0t3> ttmrichter might grep his literature library for you, but yeah, google doesn't really turn up anything.
<ZombieChicken> I think I found a paper on another possible Prolog implementation, but I was looking for actual implementations instead of just papers
<qu1j0t3> awygle: nice find
<awygle> ah
<ZombieChicken> not going to turn down a paper, though.
<ZombieChicken> For all I know, no one's done it and released it
<ZombieChicken> Well, thanks anyways folks. awygle, thanks for the PDF. That may prove interesting
<awygle> ZombieChicken: good luck :)
<ZombieChicken> ty
<rqou> anybody here familiar with kerberos/ldap?
<awygle> operationally if not theoretically
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<rqou> whee, digikey is still fucking up
<qu1j0t3> in what way
<qu1j0t3> oh the address thing
<rqou> apparently digikey really doesn't understand "wait, you live with your parents? and you're _both_ engineers?"
<rqou> I'm sure people with estranged XYZ absolutely love it
<pie___> rqou, so when do you get the boards?
<rqou> in like a month
<awygle> That seems like a really weird problem
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<awygle> lmao
<awygle> 10/10
<rqou> awygle: i assume the fun is compounded by *) my father has paid for my digikey orders (his name in bill to, my name in ship to) before and *) my father was ordering parts at the exact same time
<awygle> yeah i guess so
<awygle> but it still implies weird things about their backend to me
<rqou> "Falsehoods Programmers Believe About Addresses"
<pie___> tfw you think a machine is down because you are pinging 192.168.1.* instead of 192.168.0.*
* pie___ sighs
<rqou> i don't know why they don't have problems with dorms/apartment complexes/companies though
<rqou> oh wait they do
<rqou> i remember getting a call from a confused customer service person at digikey when i tried to get an order shipped to Foothill
<rqou> but yeah, it seems they're too smart for their own good
<awygle> pie___: argh illegal local subnets are a particular pet peeve
<awygle> err okay i guess that's not illegal
<awygle> "unexpected" then :p
<pie___> more like i forgot xD
<rqou> IPs here at $WORK confused me for a moment because they start with 172
<rqou> but not 172.16
<rqou> ie they're public addresses
<awygle> i always forget 192.168 is a /16 not a /24
<awygle> rqou: nobody uses 172.16 :p they all jump straight to 10
<rqou> i used them
<awygle> more people should use 169.254
<rqou> i usually use them for local test nets specifically because most people don't use them
<rqou> can't do that because many of my test nets were actually routable
<awygle> sure there's lots of times you can't use it but people don't even think about it
<rqou> e.g. i put equipment management interfaces under 172.16 but normal PCs under 192.168
<azonenberg_work> yeah my home network is all 10
<awygle> also tons of people are wrong about how IPv4LL, DHCP, and mDNS (and DNS-SD for that matter) interact. like what's required when.
<rqou> so both need to be non-link-local
<azonenberg_work> and i just make lots of /24s under that
<azonenberg_work> but i am trying aggressively to move to all-ipv6
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<awygle> so fe80::/10 :p
<azonenberg_work> i still need v4 for some legacy gear but i want to have most stuff that doesn't touch the internet be v6-only in the not too distant future
<rqou> ipv6 source address selection is still a bit screwy
<rqou> i probably need to start running real routing protocols :P
<awygle> i need to learn more about ipv6 than "128-bit addressing"
<rqou> or actually go write my "systemd-everythingroutingd"
<awygle> especially things like slaac that are relevant to my interests
<azonenberg_work> i use slaac exclusively
<azonenberg_work> however i do need to fix something on my network and i may need to make one or two boxes statically assigned
<azonenberg_work> tl;dr if you have the same box slaac on multiple interfaces
<azonenberg_work> its a bit tricky to figure out which route it will use
<awygle> no dhcpv6?
<azonenberg_work> especially if some of the slaac endpoints are private subnets that don't route out
<rqou> dhcpv6 doesn't disable auto-assigned addresses by default
<awygle> ooo jumbograms
<azonenberg_work> I dont like dhpv6, and this issue is only a problem if you connect to multiple subnets and some go to the internet and some dont
* awygle plots
<awygle> does ipv6 solve the checksum thing that you hate, azonenberg_work?
<rqou> and yes, i have the same problem as azonenberg_work
<azonenberg_work> and i only have one box that does that
<azonenberg_work> awygle: no, it *introduces* it
<azonenberg_work> ipv4 UDP allows you to have an optional chcksum at layer 4
<azonenberg_work> the layer-3 checksum is headers only, then layer-2 is at the end of the frame sanely
<awygle> ah i see where my confusion was now
<azonenberg_work> ipv4 TCP, and all IPv6 TCP/IP, require full payload checksums at layer 4
<azonenberg_work> And it's at the start of the packet
<awygle> oh so ipv6 doesn't have a checksum at all, but requires udp to have one? that's weird
<awygle> fuck your layers amirite
<rqou> did i ever mention the hilarity that my father once ran into with checksums?
<rqou> my father used to do a ton of "tunnel good-protocol (e.g. Ethernet) over shitty-telco-protocol-layers (e.g. T1)"
<rqou> at one point somebody was working in the simulator and was noticing that a particular checksum never changed
<rqou> but further tests showed that it was indeed correct
<rqou> turns out two of the layers both specified a checksum
<rqou> with the same size and polynomial
<awygle> lol that's great
<awygle> hm, do jumbograms actually work? udp length is only 16 bits
<rqou> afaik 9k packets do work
<rqou> but i don't usually run them
<awygle> lol "just set it to zero" that's a totally reasonable solution
<awygle> rqou: 9k isn't jumbogram, it's jumbo frame (ethernet not ip+)
<awygle> jumbogram is "ipv6 allows packets of length UINT32_MAX instead of UINT16_MAX"
<rqou> qh ok
<rqou> i don't know anything about that
<awygle> turns out they do work and you just set the udp length to 0 and use the ipv6 length plus some math
<awygle> (they also appear to have caused a lot of CVEs lol)
<rqou> ipv6 has caused an absolutely ridiculous number of CVEs
<awygle> that makes sense to me
<awygle> and i doubt it's ipv6's fault in most cases, just people making v4 assumptions and forgetting about them
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<qu1j0t3> hey rqou INCOMING DM MATE
* qu1j0t3 giggles
<rqou> lol I'm at work and don't have time for this right now
<qu1j0t3> you got their attention
<qu1j0t3> they sent me an MLP gif once
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<awygle> those "we sent you a dm" messages are so irritating
<awygle> like... they know you sent them a dm, you're just transparently trying to seem responsive for damage control
<azonenberg_work> lol yeah
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<pie___> qu1j0t3, its been brought to my attention that /r/programmerhumour has a "phone number meme"....im dying https://imgur.com/a/4f3XB
<pie___> dying inside.
<pie___> "i think the first one was actually real"
<awygle> lmao
<awygle> my favorite is the rotary phone
<pie___> very mixed feelings xD
<pie___> "angry phone input system"
<awygle> is there a safe way to printf a uint64_t?
<awygle> (without looking up what that's aliased to on this particular system with this particular compiler)
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* gruetzkopf stacked higher on "wtf, that still routes a call" stack these days
<qu1j0t3> pie___: Oh yeah i saw this a year or two ago. It's very good
<qu1j0t3> pie___: Actually this may not be the one i saw, exactly. the one i saw was even more ROFLMAO i think
<qu1j0t3> i could probably find it on our work slack
<gruetzkopf> still haven't found the number length limit on a inner-german phone call
<pie___> please do
<pie___> state machines gone wild
<gruetzkopf> well the ISDN exchanges only send up to 20 digits (really ascii chars) per message
<jn__> awygle: as far as i understand it, POSIX defines PRIu64
<rqou> afaik nobody actually uses that
<gruetzkopf> didn't find a message-count limit though, you'll get more and more messages until you send back either "yeah, ringing" or "nope, not here"
<pie___> the phone network is a series of tubes
<jn__> pie___++
* awygle is just printing it as %ull
<rqou> the man page I'm looking at suggests you can use %jd for intmax_t
<rqou> nothing specifically for int64_t
<awygle> lol protip it's %llu not %ull
<gruetzkopf> Where we're going we don't need packet switching
<gruetzkopf> Far more tube like than ietf land
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<gruetzkopf> i think building my own isdn switch would be fun
<gruetzkopf> but all that asn.1 stuff in the d-channel *shudder*
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<azonenberg_work> rqou: Sooo
<azonenberg_work> the latest entry in our saga of incompetence and craziness
<sorear> awygle: you're looking for <inttypes.h>
<azonenberg_work> our sheetrock never showed up
<rqou> wtf dude
<azonenberg_work> So i called the pro desk at the home depot to ask what was going on, they said they'd look into it
<azonenberg_work> I swung by the store a few minutes ago to buy some unrelated stuff and stopped in to see if they had any updates
<sorear> awygle: (although %jd is probably a more reasonable way to do it than the standard way)
<azonenberg_work> Turns out, they faxed the purchase order (yes, the vendor still uses faxes) over to the vendor's corporate office
<azonenberg_work> Corporate then lost the PO and never forwarded it to the local warehouse that was going to fullfill it
<rqou> how do you keep managing to use the most assbackwards vendors?
<azonenberg_work> not entirely sure
<azonenberg_work> i think its the whole industry
<azonenberg_work> being fscked pretty thoroughly :p