<rqou> yup, a rechargable electric dragon loli
<rqou> must protec, no lewd
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<ZombieChicken> wtf
<ZombieChicken> why is this channel discussing electric dragon lolis?
<sorear> rqou is extremely into it for some reason
<Ultrasauce> I take it you're one of those luddites that only accept the mechanical ones?
<rqou> lol
<sorear> keeps wanting to name the successor to the maxv work after them
<rqou> blame pie__
<rqou> pie__ is the one that actually suggested these names
<rqou> also, Lucoa isn't an electric dragon loli :P
<rqou> (for the unlikely-to-actually-happen arria RE project)
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<pie__> wha tno
<pie__> this is totally not ALL my fault
<pie__> for the record i do do normal things with my life
<rqou> "normal"
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<pie_> :p
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<cr1901_modern> > ZombieChicken: why is this channel discussing electric dragon lolis?
<cr1901_modern> Because ##openfpga is a channel about anime, didn't you read the rules :P?
<fseidel> darn, I must have found the wrong channel :-P
<Zorix> could be much worse...
<fseidel> rqou tells me you guys sometimes get a little off topic, this has been an interesting channel to watch
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<rqou> lol, quartus won't let me synthesize a design with zero logic
<fseidel> I've had it accidentally synthesize designs that should have had logic but it optimized it out due to missing I/O
<fseidel> what are you trying to synthesize?
<rqou> literally module test() endmodule
<rqou> you at least need one wire assigned to a 0
<fseidel> interesting
<fseidel> I think my pin assignments file pulls a few I/O pins to 0 so it doesn't ever give me that error
<rqou> hmm, for me it bombs out on quartus_map before getting to that point
<rqou> the anti-footgun features in quartus make reverse engineering harder :P
<rqou> hmm, i can't seem to actually get pull-up resistors to generate at all
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<fseidel> what version of quartus?
<rqou> 18 lite
<fseidel> I've tried on 12 Pro and 17 Pro
<rqou> do i have to assign something useful to the pin?
<fseidel> I don't remember
<rqou> O_o why does "Pad View" exist?
<rqou> so apparently the die has 80 io pads but no package does?
<rqou> arrgh, how come in general i can't figure out how to get any IO features to work?
<rqou> ok, finally got it to enable
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<azonenberg> rqou: pad view? you mean it shows package pins for pin planning? or what
<rqou> yes, but labeled as "bond pads" rather than io pins
<azonenberg> interestnig
<azonenberg> in other news we almost finished insulating the lab today
<azonenberg> and ordered sheetrock
<rqou> also revealing that there's an extra one that no package exposes
<azonenberg> not arriving until after the 4th though, due to the holiday messing with scheduling
<azonenberg> whatever that monday is
<rqou> oh btw, i just figured out why "some bit" kept getting set whenever i used an IO pin
<rqou> it turns out that bit is the "fast slew rate" bit
<rqou> also, this chip has programmable drive strength, so fuzzing that will be fun
<rqou> azonenberg: any idea why the lower drive strength causes _two_ bits to get set?
<rqou> the output driver structure must be complicated AF
<rqou> azonenberg: how do you think the output drivers work? the output current can be 2/3/4/6/7/8/14/16 mA, but each io standard only has two strengths
<azonenberg> what do you mean, each only has two?
<rqou> so 3.3v lvttl can only use 16/8 mA
<rqou> 3.3v lvcmos can only use 8/4 mA
<rqou> 2.5v lvttl/lvcmos can only use 14/7 mA
<rqou> 1.8v lvttl/lvcmos can only use 6/3 mA
<rqou> 1.5v lvcmos only 4/2 mA
<rqou> and 1.2v lvcmos only 3 mA
<rqou> and i don't know how pseudo-differential pairs work
<azonenberg> Soo
<azonenberg> 3.3 16/8 vs 2.5 14/7 makes sense to me
<azonenberg> i'm gonna guess they're the same pair of drivers
<azonenberg> But at 2.5V given the same Rds(on) you get less current than with 3.3
<rqou> why does lvcmos3.3 have a 4ma option?
<azonenberg> i'm thinking there's 3 drivers
<azonenberg> one 16, one 8, one 4 at 3.3V
<azonenberg> But for timing reasons lvcmos/lvttl have different legal configs
<azonenberg> Then probably 1.8V switches to a differnet driver with thinner gate oxide but less drive strength? not sure
<azonenberg> I think the low voltage 6/3 are the two base drivers then 4/2 are the same at reduced voltage
<azonenberg> then 3 is the 4 at reduced voltage
<rqou> and then emulated lvds/rsds?
<azonenberg> Probably just opposite polarity lvcmos drivers
<azonenberg> is there an external resistor or something to provide common mode biasing?
<rqou> i think so?
<rqou> idk how it works
<azonenberg> i know thats how some lattice parts are for emulated lvds
<rqou> i don't even know if it uses one or two output muxes
<azonenberg> my guess? it uses two iobs and a fabric inverter :p
<rqou> lol
<rqou> which is free, so...
<rqou> azonenberg: btw, why do you think this option exists in quartus? "Allow voltage overdrive for LVTTL/LVCMOS input pins"
<azonenberg> What does it do exactly?
<azonenberg> allow lvcmos33 input in a lvcmos25 bank?
<rqou> "Specifies whether the Fitter allows input pins with LVTTL or LVCMOS I/O standards to be placed inside an I/O bank with a lower VCCIO voltage than the voltage specified by the pins. Overdriving the I/O bank results in higher leakage current, which can cause the design to not function as intended."
<rqou> yeah, i think so
<rqou> also, the datasheet has this funny warning "When V CCIO = 3.3 V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected."
<rqou> sounds quite a bit like a "whoops" :P
<azonenberg> not a whoops
<azonenberg> that sounds normal for a cmos input buffer
<rqou> but it doesn't happen for any other pairs?
<azonenberg> it's probably high enough to turn on the nmos comfortably
<azonenberg> but far enough below 3.3 that it starts to turn on the pmos too
<rqou> why doesn't 1.2v trigger this problem?
<azonenberg> Probably it uses a different set of buffers
<rqou> oh yeah lol 1.2v isn't allowed if vccio is 3.3v
<azonenberg> most cmos processes i've seen have 2.5/3.3 be one buffer and 1.2 and below be another
<rqou> there's this giant table explaining what allows what
<rqou> so vccio of 3.3 allows an input down to 2.5
<rqou> vccio of 2.5 only allows down to 2.5
<rqou> vccio of 1.8 allows down to 1.5
<rqou> vccio of 1.5 allows down to 1.5
<rqou> and vccio of 1.2 allows only 1.2
<rqou> oh, it doesn't allow up to 3.3v any more if vccio is 1.2
<azonenberg> Yeah makes sense
<rqou> whee, this part does not require special power sequencing apparently
<rqou> and you can drive io pins before powering up the device
<rqou> no parasite power through esd clamps :P
<azonenberg> most xilinx parts dont either
<azonenberg> well, idk if they like driving io before it turns on
<azonenberg> but no rules re sequencing rails
<rqou> iirc coolrunner-ii actually allows this too
<rqou> it apparently is/was a commonly-requested CPLD feature
<rqou> hmm, datasheet has references to "The 3.3-V tolerance control circuit"
<rqou> aww, the device won't power up if vccio isn't present
<rqou> azonenberg: does coolrunner-ii do that?
<awygle> still is, it's hugely useful
<azonenberg> iirc behavior is unspecified if vcco is unpowered? cant remember
<azonenberg> i know empirically it seems to work :p
<azonenberg> i use a coolrunner as a level shifter on my jtag dongle
<awygle> that kind of stuff is like half the use cases for cplds iiuc
<azonenberg> and it just ties vcco to vref
<azonenberg> But i dont know if the cpld resets when i disconnect the DUT
<azonenberg> never tested
<rqou> arrgh, Fiora nerdsniped me and now i want to try the lcamtuf resin casting procedure again
<rqou> but but but i already have enough stuff going on
<rqou> azonenberg: random: i really want an airtight glovebox
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<azonenberg> rqou: me too
<azonenberg> with positive pressure hepa ventilation
<rqou> no argon/nitrogen fill?
<azonenberg> i'd mostly want it for homecmos stuff and/or die imaging without particles landing on the stage during long microscope runs
<azonenberg> So, basically a desktop cleanroom
<rqou> yeah, that too
<azonenberg> Not for inert atmosphere etc
* rqou needs a giant warehouse
<azonenberg> That too
<azonenberg> And an army of evil minions
<rqou> well, you should finish your current friggin house first
<azonenberg> Lol
<azonenberg> well, sheetrock is coming in a weekish
<rqou> then maybe if your $WIFE actually nags you enough you can have an evil minion :P
<azonenberg> So we have until then to finish insulating and pass inspection
<rqou> but i'm telling you, that's going to just turn into a huge timesink instead
<azonenberg> Then once we start sheetrocking my tentative plan is to have her installing the 275 electrical outlets by day when i'm at work
<azonenberg> then hang rock by night together
<azonenberg> hopefully finishing before we have to move out
<rqou> "hopefully"
<rqou> i sure hope you've got a backup plan for that
<azonenberg> We will definitely have at least a couple of rooms rocked by the time we have to move
<azonenberg> So we can pile all our stuff in them
<azonenberg> Then couch surf, get a short term apartment, etc if the house isnt finished
<azonenberg> Based on my current timeline i expect it will be tight but i think we can finish, what i am more worried about is that the current timeline has no room for me to pack up the alb
<azonenberg> lab*
<azonenberg> And moving this will be nontrivial
<azonenberg> Especially in a couple of days
<azonenberg> i spent months packing last time around
<azonenberg> So my thinking is, as soon as we get a couple of rooms rocked and wired (maybe the office? it's big and doesnt have a ton of wall space per square foot) start piling boxes up in there
<azonenberg> make absolutely sure we're moved out on time without rushing too much
<azonenberg> Then use all remaining time to get as close to livable as we can
<azonenberg> And see where we end up
<rqou> i'm seriously not seeing how you could have possibly been done a month ago
<azonenberg> The original timeline didn't include insulation removal/replacement
<azonenberg> that cost us a TON of time
<azonenberg> so far we spent this entire week insulating the 1st floor and part of the 2nd,
<azonenberg> we lost about a month earlier removing the old stuff from the attic etc
<azonenberg> Then just other things compounding and adding unexpecteed delays
<rqou> why does _installing_ insulation take so long?
<azonenberg> Cutting holes for electrical boxes
<azonenberg> Cutting to length (the upstairs is slightly less than 8 feet high, apparently slightly shorter ceilings were the thing in the 70s) so every batt has to be cut short by a few inches
<azonenberg> All of the half-height walls need to be insulated too
<azonenberg> Which means lots of tiny pieces on top
<azonenberg> Then a lot of the legacy framing has weird stud spacing that requires pieces to be cut lengthwise (not 16" pitch)
<azonenberg> we have a good system going where i figure out the rough measurement for a wall, then have ally do all of the cuts to length
<azonenberg> then i hang all of the pieces that don't have to dodge electrical boxes
<azonenberg> in parallel
<azonenberg> then once she's done with the rough cuts for a bunch of stuff i start doing electrical box cutouts
<azonenberg> Then there's delays moving materials, reloading the staple gun
<azonenberg> Replacing the staple gun once, because it broke :p
<rqou> how the heck have you broken basically every tool at this point?
<azonenberg> i've had this staple gun for years
<azonenberg> But apparently 10k+ rounds through it was enough
<rqou> i hope the next things to break don't include human bodies :P
<azonenberg> I still dont know what happened to it
<azonenberg> when i fired it in open air, i saw a staple fly away
<azonenberg> But when i pressed it against the wall, there was a click and no staple
<azonenberg> maybe not hitting hard enough? idk
<azonenberg> the new one works fine (and also can drive tiny brad nails for trim when we get to that point)
<azonenberg> oh and changing blades on the razor knife, that's a big one
<azonenberg> Cutting glass on a concrete surface does wonders for blade sharpness :p
<azonenberg> we go through several blades per hour
<rqou> aren't there special blades for this?
<azonenberg> Nope, just a normal utility knife
<rqou> what do pcb fabs use to cut fr4?
<azonenberg> upstairs we cut on the plywood floors, so they dont dull quite as fast as scraping concrete constantly
<azonenberg> but the glass still dulls them
<azonenberg> Fabs normally use carbide
<azonenberg> but it's also many kRPM
<azonenberg> and cutting a solid material, not fibers in air
<azonenberg> rotary cutting fiberglass without resin isnt gonna work
<azonenberg> oh, the other thing that takes time is doing all of the plywood pieces for the half-height walls
<azonenberg> Rather than putting just drywall on top i'm putting down 3/4" plywood to provide a more load-bearing surface
<azonenberg> so we can use them as a shelf capable of supporting more weight
<azonenberg> But that means measuring and cutting and screwing down
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<rqou> azonenberg: best bitstream RE tool: eog :P
<azonenberg> lolol
<azonenberg> if it works
<rqou> i'm not even joking, i use it a lot
<rqou> maybe just my style?
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<rqou> wat
<rqou> bank 1 can't support 1.2 v
<rqou> hmm wat
<rqou> azonenberg: by default (highest drive strength?) nothing changes as i change the io standard
<azonenberg> that makes sense, up to a certain voltage range where i'd expect a bit to flip for selecting HVT or LVT
<azonenberg> in the buffers
<azonenberg> But for the most part, within a range of similar voltages
<azonenberg> i'd expect just timing analysis changes
<rqou> no, i don't see that either, all the way down to 1.2 v
<azonenberg> ok now that's weird
<rqou> yeah, something seems fishy
<rqou> ok, azonenberg: notes dump incoming
<rqou> i'm considering lvttl 16ma as baseline
<rqou> lvttl 8ma: two bits get set
<rqou> lvcmos 8ma: same as lvttl 16ma
<rqou> lvcmos 4ma: same two bits get set
<rqou> 2.5v 14/7 also do the same thing
<rqou> 1.8v 6/3 also
<rqou> 1.5v 4/2 also
<rqou> and 1.2v no bits set
<rqou> so somehow it seems the "low" current for every io standard sets two bits
<rqou> something seems not quite right about this
<rqou> azonenberg: thoughts?
<daveshah> FWIW ice40 has no bitstream changes for different IO standards - except LVDS of course
<daveshah> But it doesn't have drive strength setting either
<daveshah> ECP5 has ridiculously complicated IO settings, including some per bank VccO bits
<daveshah> Haven't fuzzed them completely, but enough to do bitstream gen for any common config right now
<rqou> something really weird is that 3.3v lvcmos 8ma has the same settings as 3.3v lvttl 16ma
<rqou> that just seems totally not right
<daveshah> Yeah, that's really strange
<daveshah> LVCMOS and LVTTL are identical on ECP5
<daveshah> Just syntactic sugar basically
<azonenberg> daveshah: same on xilinx i think, it just changes timing parameters
<daveshah> But I think the drive strengths are only nominal values anyway
<azonenberg> for the different vcc range
<azonenberg> for coolrunner there's no drive strength
<azonenberg> all you have is one bit for HVT or LVT on the io buffers
<azonenberg> per bank
<daveshah> Yeah, ECP5 has way more options than that
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<azonenberg> yeah i imagine 7 series is a lot more complicated too :p
<daveshah> I think it was probably sensible of clifford to leave that for now
<daveshah> They also have quite intricated clocking and PLL/MMCM stuff
<rqou> hmm
<rqou> azonenberg: what if the actual current numbers are just a lie to placate "old-school" designers?
<rqou> e.g. "yes, we can drive an equivalent fanout that a ttl part that sources 20mA can drive"
<daveshah> Almost certainly
<daveshah> I don't think they are constant current drivers or anything
<daveshah> Does the datasheet say anything?
<rqou> "The output buffer for each MAX V device I/O pin has two levels of programmable
<rqou> drive strength control for each of the LVTTL and LVCMOS I/O standards."
<rqou> and it does give numbers in mA
<rqou> hmm, but there are only four sets of output current vs voltage curves
<rqou> two each for i_ol and i_oh, and then each one has just high and low
<Adluc> you have my respect guys for dissecting bitstreams :D
<rqou> of course there are then multiple curves plotted on the graphs
<rqou> but this seems to support that there's only two settings
<rqou> and the numbers are just to make "old-school" designers happy
<daveshah> The curves go way beyond the nominal drive strengths clearly
<rqou> yes definitely
<daveshah> That supports what I heard previously that using drive strength to drive LEDs directly etc is a bad idea
<rqou> so i'm definitely leaning towards "the numbers are nominal for fanout limit calculations"
<rqou> for people old enough to have ever worried about that on discrete parts
<rqou> now it's just a bit strange why there are _two_ bits for this
<rqou> oh well
<rqou> guess we probably need decap for that
<azonenberg> rqou: yeah they are definitely not fancy active current limited drivers
<azonenberg> imo they're probably just different numbers of fingers on the same buffer
<azonenberg> Greenpak makes this a bit more explicit
<azonenberg> they have config bits for enabling 1x, 2x, or 4x drive strength
<rqou> yeah, that's what i think too
<rqou> but this just has 1x and 2x
<rqou> but then they have to lie and make old 74xx-era designers happy and give them some numbers :P
<azonenberg> The numbers are probably something along the lines of "X mA into a 50 ohm load"
<rqou> that doesn't explain why lvcmos33 and lvttl33 get different numbers
<rqou> ooooh wait i think you're right
<rqou> but in a dumb, roundabout way
<daveshah> Is it do with load for a specified Voh/Vol
<rqou> ^
<rqou> yeah, that
<daveshah> That might change for cmos and ttl
<rqou> that's the only thing that changes
<rqou> "X mA into a Y ohm load while maintaining Voh/Vol appropriate for this io standard"
<azonenberg> yeah
<rqou> azonenberg: why do you think there are _two_ bits?
<azonenberg> Thats why i said earlier re timing analysis
<azonenberg> rqou: Not really plausible to tell w/o decap
<rqou> i wonder if they have to do anything on the input path
<azonenberg> conjecture: one is enabling the driver and the other is enabling some kind of bank-level local power rail
<azonenberg> Or tha
<azonenberg> that*
<rqou> no, two unique bits per output
<azonenberg> Maybe the ibuf isnt disabled when you're using an output
<azonenberg> So they need to select HVT if you're using too high a VCCO
<rqou> no, it's not correlated with VCCIO
<rqou> the "low power" setting just always has both bits set
<rqou> oh btw azonenberg: i have one mystery bit in the middle of each logic tile (that never changes). want to start pulling guesses out of <redacted> as to what it may be? :P :P
<rqou> it's special because it's set to 0
<azonenberg> some kind of die test feature?
<rqou> hmm
<rqou> i thought altera normally used test pads for that?
<rqou> at least in your ancient decaps
<azonenberg> i dont remember doing any altera decaps
<rqou> there's a product term cpld decap on pr0n
<azonenberg> other than matthiasm's massive stratix
<azonenberg> oh
<azonenberg> yeah that was me, the epm3064
<azonenberg> but i never did any analysis on it
<azonenberg> iirc it was the same weird tsmc process at those silicon image GPUs?
<azonenberg> strange looking non-uniform thickness overglass
<rqou> wait, tsmc?
<rqou> they were using tsmc that long ago?
<rqou> alright, afaict "input" related features (ie schmitt trigger at least) are in the "fabric" part of the bitstream
<rqou> not the "padring" part
<azonenberg> pretty sure this was tsmc 350nm
<azonenberg> or thereabouts
<azonenberg> yeah it's tsmc 350 originally, then shrunk to 300 nm
<azonenberg> might have just been a lens swap on the stepper or something with the same mask set?
<rqou> yeah i guess that still worked at that time
<rqou> but wait, that makes the chip faster
<rqou> which might screw up some (buggy) designs
<azonenberg> speed grades in general set bounds
<daveshah> I think they did the same from CycIII to CycIV, given it was only a 5nm difference or something and the JTAG ID didn't change
<azonenberg> not actual values
<azonenberg> And they might tune some other parameters to roughly match performance
<azonenberg> the main reason for a small shrink like that is improving dies per wafer and cutting fab costs
<azonenberg> So presumably the NRE has to be pretty minimal
<rqou> but still, you know some missile or medical device or something else infamous for high reliability designs and yet shit code quality will break
<azonenberg> once you have the original tapeout done
<rqou> i guess that's what PCNs are for :P
<rqou> also, i thought optical shrinks don't work anymore at near 65nm?
<rqou> so CycIV might have needed some tweaking?
<daveshah> maybe
<daveshah> it just seems like such a lot of effort for a small change
<daveshah> but maybe the new process was cheaper or the old one was discontinued or something
<rqou> i thought 65nm is like never going to get discontinued?
<azonenberg> lol
<rqou> just like 180nm isn't
<azonenberg> i think even 180 is never going to die
<azonenberg> ... exactly
<azonenberg> because it's cheap, and 80% of products dont need the increased density
<azonenberg> it would not surprise me if (say) 45 or 28 nm lines got shut down before 180
<azonenberg> Because all of the leading edge stuff by that point will be on 5nm or whatever the new hotness is
<azonenberg> but cheap stuff is still on 180 :p
<daveshah> reckon 28nm will stay for a while
<daveshah> new non-power-constrained SoCs still seem to be using it
<azonenberg> yeah the specific numbers are irrelevant
<azonenberg> point is, i could see 180 staying longer than some more modern nodes
<rqou> so azonenberg, random speculation time: when do you think we will start seeing NC-FETs in production?
<azonenberg> we might end up with kind of a 3-tier process hierarchy
<azonenberg> ~180 for cost optimized, ~28 for midrange SoC type stuff, and $TINY for leading edge CPUs, GPUs, FPGAs, flash, DRAM, etc
<azonenberg> rqou: wtf is a nc-fet?
<azonenberg> numerically controlled? :p
<rqou> negative capacitance fet
<azonenberg> wut
<azonenberg> how does that work
<rqou> you can add doped HfO as a ferroelectric into the gate stack
<azonenberg> so what does it do
<azonenberg> whats the actual end effect?
* azonenberg is trying to figure out what negative C actually means
<rqou> um... iirc it make Vt lower?
* rqou is bad at device physics
<azonenberg> negative resistance makes sense to me, in terms of a nonlinearity where increasing voltage causes less current flow and vice versa
<azonenberg> a good example of that would be a SMPS
<azonenberg> trying to output a constant voltage/current
<azonenberg> as Vin drops, I goes up to compensate
<azonenberg> which leads to a negative I/V slope
<rqou> right, "one can achieve the same charge density in the channel with a smaller voltage at the gate"
<rqou> herp derp i am real electrical engineer
<azonenberg> huh
<azonenberg> and i've taken... 3? EE classes
<azonenberg> i forget
<azonenberg> ACHD and one or two on networking and protocol :p
<rqou> as for how does it work? idk ferroeletrics are fucking magic
<azonenberg> and protocols*
<azonenberg> heck, i dont even have an engineering degree
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<rqou> so of course the capacitance isn't just purely negative
<rqou> it's nonlinear and negative around an operating point
<azonenberg> well most negative resistors arent negative forever either
<azonenberg> But there is a point in the I/V curve with negative slope
<rqou> as for how to simulate this, well somebody at berkeley just recently completed a phd on how to do that :P :P :P
<rqou> so don't ask me
<azonenberg> Lol
<rqou> but yeah, apparently this idea suddenly became not crazy when it was found that doped HfO was a ferroelectric
<rqou> apparently hafnium was already used in various dielectric materials and so this is cmos-compatible
<azonenberg> Yeah
<rqou> unlike pzt which is an annoying ceramic that just makes a mess everywhere
<azonenberg> Reminds me, I think i still have some Ta2O5 sol-gel in the lab
<azonenberg> from years ago
<azonenberg> it's way past the expiration date but might still be usable :p
<azonenberg> i mean it's tantalum chloride in ethanol
<azonenberg> there's nothing in there that would really destabilize
<rqou> did you have to pay a warlord for it? :P
<azonenberg> No, i paid emulsitone for it
<azonenberg> (idk if they still make it, lol)
<rqou> but did they end up paying a warlord? :P
<azonenberg> That i dont know
<rqou> hey, intel specifically has a "Conflict Free: Yes" entry in ARK
<rqou> i wonder if you can filter for No :P
<azonenberg> Support your local African warlords! Boycot conflict-free components
<azonenberg> :p
<azonenberg> Anyway the big problem i ran into it is that Ta2O5 is *super* chemical resistant
<azonenberg> the only thing that really eats it is hot HF
<rqou> RIE?
<rqou> or does that not work either?
<azonenberg> didnt have it
<azonenberg> didnt try
<azonenberg> i tried doing lift-off and the solvent of the sol-gel ate my resist
<rqou> lol
<azonenberg> i tried wet etching with a photoresist mask and the hf undercut my resist
<rqou> lolol
<azonenberg> my original use case was MEMS
<azonenberg> i wanted to do a hardmask for a koh etch
<azonenberg> and pecvd nitride wasn't DIY-friendly enoguh
<rqou> you don't strictly need a hardmask for that?
<azonenberg> so i wanted to try to find a hardmask i could apply by spin coating
<azonenberg> Thermal oxide is etched pretty rapidly by koh
<azonenberg> i wanted to do seriously deep, like through-wafer, etching
<rqou> ah ok
<azonenberg> one of my designs called for lithographically dicing a wafer into 1cm square dice
<azonenberg> then leaving a full thickness ring around each die
<rqou> you know you can just do that with a scribe, right? :P
<azonenberg> with the middle thinned to a ~10 um membrane
<azonenberg> then putting a comb drive in that membrane
<rqou> oooh
<rqou> ok, you can't do that
<rqou> wait, is this why you were a weirdo and not using a 100 wafer like everybody else?
<azonenberg> I was going to use <110> oriented wafers which give you super steep vertical sidewalls
<azonenberg> exactgly
<azonenberg> With a <110> wafer the <111> planes are vertical
<azonenberg> So, at least in one direction
<azonenberg> you can get chemically limited super-steep vertical trenches
<azonenberg> no RIE required
<rqou> yeah, i'm aware of this process
<rqou> funny, i thought you hated wet etches in general though?
<azonenberg> "Fabrication of very smooth walled and bottomed silicon microchannels for heat dissipation of semiconductor devices" or something along those lines
<azonenberg> This was circa 2010-2011
<azonenberg> that i was doing this work
<azonenberg> I didnt have access to any plasma stuff
<azonenberg> this was the height of homecmos
<azonenberg> i was using mems as a testbench for litho etc before moving on to trying to make an IC
<azonenberg> But i needed better lab facilities
<azonenberg> and had no budget
<azonenberg> then grad school happened
<rqou> sam zeloof didn't need amazing lab facilities :P
<azonenberg> lol
<azonenberg> he also bought half a fab secondhand
<azonenberg> i was trying to use commodity materials and supplies that were accessible to a well-funded hobbyist or moderate sized hackerspace
<azonenberg> Hence trying to go all wet chem with minimal UHV and minimal use of extreme hazmats
<rqou> at this point, "half a fab" fits that criteria too :P
<azonenberg> for example, rather than dealing with silane
<rqou> according to whitequark UHV isn't that hard :P
<azonenberg> i wanted to see if i could do a-si gates by sputtering a silicon wafer target
<azonenberg> in argon
<azonenberg> then adding some oxygen to the mix to try reactive sputtering SiO2
<azonenberg> again, no LPCVD of SiH4 + O2
<rqou> wtf
<azonenberg> just a solid silicon wafer, argon, and oxygen
<rqou> or you can just figure out a way to get/make silane?
<azonenberg> all ingredients that are (relatively) harmless to store
<azonenberg> the point was to avoid dealing with pyrophoric/super-toxic gases
<azonenberg> same reason i was goign to use spin on dopants instead of implanting with arsine or phosphine or all those nasty gases
<rqou> you mean you don't want fires that leave ultrafine sand in their wake? :P
<azonenberg> let's just say the sand isnt my biggest concern
<azonenberg> :p
<rqou> silane isn't considered particularly toxic
<azonenberg> i was more concerned about dealing with pyrophoric materials
<azonenberg> It's also health hazard 4 on the nfpa diamond iirc
<rqou> huh, apparently producing silane is also a pain in the ass
<rqou> nope, just 2 according to wikipedia
<azonenberg> ah ok i misremembered
<rqou> arsine is probably a 4 :P
<azonenberg> but like i said, the spontaneous combustion was the bigger concern
<azonenberg> i wouldnt mind having a cylinder of something like argon around
<azonenberg> as long as the room was big enough that venting it all relatively fast wouldn't decrease the O2 level too horribly
<azonenberg> And i wouldnt mind an O2 tank, a small leak is unlikely to present a massive fire hazard
<azonenberg> it'd dissipate fast and you'd just have slightly oxygenated air
<azonenberg> Obviously you'd have to be careful about the tubing etc
<rqou> huh, apparently silane _is_ toxic
<rqou> but i guess not too much
<rqou> apparently germane is more toxic
<azonenberg> at RPI, all of the "fun" gases
<azonenberg> silane included
<azonenberg> were run in double-walled tubing
<rqou> according to wikipedia silane has a "repulsive" odor
<azonenberg> thy had low pressure inert gas in the space between the walls
<rqou> i wonder how they found that out?
<azonenberg> sorry, i meant to say high pressure
<azonenberg> relative to the toxic gas
<azonenberg> So if there was a breach of the inner tube, you purge inert gas into the hazmat and not the other way around
<azonenberg> (and ring alarms from the pressure change)
<rqou> yeah, that makes sense
<azonenberg> a breach of the outer tube would also trigger alarms, while not leaking the gas
<azonenberg> My point is, a tank of argon doesnt require that kidn of precautions
<rqou> so don't be like dupont and forget to replace their hoses carrying phosgene?
<azonenberg> :p
<rqou> <insert link to CSB video here>
<azonenberg> Pretty sure i watched that one
<azonenberg> actually i know i did, i watched everything on the CSB youtube a year or so ago
<azonenberg> Anyway, the idea was that if i can get adequate quality silicon thin film by sputtering a wafer in argon
<azonenberg> and optionally adding oxygen or nitrogen
<rqou> in general, how the heck do people find out and describe the odors of "fun" compounds anyways?
<azonenberg> (or just air, to get oxynitride with a somewhat-predictable ratio)
<azonenberg> then there'd be no need for nasty hazmats
<azonenberg> in gaseous form
<rqou> you're no fun :P
<azonenberg> the goal was to make 3% HF the nastiest chemical you had to work with
<rqou> laaaaame :P
<azonenberg> aanyway i need to sleep so i can (hopefully) finish insulating the first floor tomorrow
<rqou> whelp, this is going to be a problem
<rqou> apparently the io pin input delay is occasionally _required_ to meet hold time
<rqou> so writing my own tool is going to require at least rudimentary timing analysis to work first
<daveshah> hmmm
<daveshah> I don't think any open tools have really worried about hold time before
<daveshah> icetime certainly doesn't bother with it
<rqou> the docs explicitly call this out as a problem that quartus will automatically handle for you
<rqou> I'll have to investigate more tomorrow, but the datasheet at least gives a naive timing model based on adding up path elements
<rqou> which is probably good enough?
<daveshah> yeah, that would be fine for something like that
<daveshah> just run basic topological timing analysis after par and set that bit accordingly
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<rqou> digshadow: can i present max v re at mtvre?
<digshadow> rqou: you mean july 11? sure, give me title and estimated length
<digshadow> and be aware that its back to mountain view
<rqou> title can just be "Documenting the Altera MAX V bitstream format"
<rqou> idk about length, what's a normal length for a talk? 1 hr?
<digshadow> rqou: how much content do you have?
<digshadow> I'll put you in for 40 min talk + question time
<rqou> probably going to be a lot
<digshadow> but make it 10 min if thats all you need for a quality talk
<rqou> ok, sounds good
<rqou> there's definitely more than 10 minutes of content
<rqou> so yeah, 40 min sounds good
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<Adluc> Hello guys, is it possible for ice40 to have something like bootloader, e.g. multiple bitstreams on one flash and make it boot default one (lets say first), that one will download bitstream to some offset to the shared flash and force reload?
<Adluc> with that offset
<daveshah> Yes, have a look at the tinyfpga usb bootloader for example
<Adluc> daveshah: thanks!
<daveshah> You can have up to four bitstreams in SPI flash, and use the SB_WARMBOOT primitive to select and reboot
<Adluc> excellent !!!!!!
<tinyfpga> It’s used in the TinyFPGA BX: https://www.crowdsupply.com/tinyfpga/tinyfpga-bx
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<Adluc> what have you done, showing me such boards and crowdsupply
<Adluc> epic
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<sorear> that's the project clifford applied to for symbiflow funding but was rejected from
<pie_> lol rekt
<pie_> that seems kind of dumb though
<pie_> pardom my phrasin gbut they should have probably thrown him a couple grand and theyd be well off
<pie_> he's got results on the table no?
<sorear> dunno, seems like most of the recent work is secret
<pie_> *pardon my phrasing
<pie_> what do you mean?
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<awygle> yeah, that's one of those things where... i mean, the way government contracts are awarded is bad, but it's so famously bad i'm surprised whenever anybody is still upset about it.
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