<mithro> cr1901_modern: ping?
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<mithro> Does anyone have a VIM syntax highlighting for SDF files?
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<mithro> Can you specify timing constraints with PCF?
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<mithro> I also don't quite understand the LogicCell40 model - is lcout == lut clocked out? IE when using the ff and ltout when using the output directly?
<mithro> They don't really map to anything in the bitdocs -- They have lutff_X/cout, lutff_X/lout and lutff_X/out ....
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<rqou> ok, i fuzzed all neighbor links and outputs from the row IOs
<rqou> i think this is finally everything in the connectivity graph?
<rqou> 16348 routing pairs
<rqou> unless something is still missing
<mithro> rqou: Want to start importing into the arch-defs?
<rqou> not yet
<mithro> rqou: What more do you need?
<rqou> flip-flops, for one
<mithro> rqou: You probably don't need the actual bits for the bitstream to start getting things into vpr
<mithro> rqou: Do you have a description of how the switch box / routing in the part works?
<rqou> azonenberg: ping?
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<azonenberg> ack
<rqou> how'd your SAR mission go?
<rqou> aaargh i _just_ discovered even more weird interconnect paths
<rqou> the journey never ends
<rqou> azonenberg: i think i need a better approach?
<rqou> otherwise it seems like a perpetual game of "oh shit this is also connected to that"
<azonenberg> Lol
<azonenberg> fund my silicon reversing projects that ioa isn't
<azonenberg> and develop tools to re the die and figure out 100% of legal routes? :p
<rqou> lol i wish i had that kind of money
<rqou> anyways, i just discovered that lut outputs can feed into the local tracks in a tile that _aren't_ the special designated ones for connecting luts to other luts
<rqou> seems this chip has a lot of "oh, we have something extra, what should we put here?" features
<mithro> ioa?
<rqou> wtf
<rqou> azonenberg: lut number 4 has a cascade connection to lut number 5
<rqou> but these aren't physically adjacent
<rqou> how does that work?
<rqou> azonenberg: so the physical ordering of luts is 01234 98765
<rqou> but somehow a wire runs from 4 to 5
<rqou> any thoughts as to wtf they might be doing?
<mithro> rqou: Could it be something like -> 01234\n98765 (IE 0 above 9, 1 above 8, etc?)
<mithro> rqou: IE Two rows?
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<rqou> low-res die photo i have says no
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<azonenberg> yeah a 2-col tile makes sense
<rqou> but that doesn't match the photo i'm looking at
<azonenberg> idk? just an idea
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<openfpga-github> [Glasgow] awygle pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/7c3203c126e7444981d5405d7d6fcd1db53bbbc5
<openfpga-github> Glasgow/master 7c3203c awygle: Add edge-rate control resistors on FPGA side.
<rqou> o/ awygle
<awygle> o/ rqou
<rqou> hey awygle want to build me a pcb? :P
<awygle> whitequark: that might have some ugly silk, i'll do a cleanup pass in the morning
<awygle> what kind?
<rqou> max v breakout
<rqou> yes, or i can just do it myself :P
<awygle> lol
<awygle> if you haven't done it in 1-2 weeks, ask me again
<awygle> gonna try to get glasgow c to a reasonable state by then
<awygle> sounds like you're making good progress
<awygle> despite all the wtf-ery
* awygle zzz
<rqou> azonenberg: any thoughts as to how to proceed now?
<rqou> i've fuzzed what i thought were all the missing bits from before
<rqou> so other than constantly discovering new features, i think the focus should shift to "the actual logic stuff?"
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<rqou> ok, there are self-connections in the ios too
<rqou> apparently only in the rows
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<rqou> hmm, i'm still incredibly suspicious of how the column local interconnect never can get the "one bit only" mux setting
<rqou> whelp, looks like i was right to be suspicious because there is something weird going on with it
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<rqou> whelp this is a problem
<rqou> the mystery bit in the column IO local interconnect doesn't seem to correspond to anything in the routing output
<daveshah> mithro: the timing cells match Lattice's exactly, because that is how the re for that worked
<daveshah> Have a look at the LogicCell40 model in Icecube2
<daveshah> ltout is lout and lcout is out
<daveshah> Normally you will use lcout
<daveshah> Even if the DFF is disabled
<daveshah> ltout is just for LUT cascade
<daveshah> logic_op are used inside IO tiles, for the outputs from nearby logic tiles. neigh_op are used everywhere else
<mithro> daveshah: So the DFF doesn't affect the timing?
<daveshah> Of course it does
<daveshah> The clocked values are used when the DFF is enabled
<daveshah> The SETUP and HOLD checks, and the clock to lcout delay
<daveshah> The combinational delays from in to out are then ignored when the DFF is enabled
<mithro> daveshah: Okay, thanks!
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<rqou> o/ pb_
<rqou> pb_: what exactly is your interest in max v re?
<rqou> are you working on your own thing?
<pb_> rqou, seen message from morning?
<rqou> yeah, i didn't really understand what you were trying to explain
<mithro> daveshah: ltout is lout and lcout is out <-- That is the key detail I needed
<daveshah> mithro: yeah, although I think it is fairly clear (this is Lattice's inconsistency anyway, nothing to do with icestorm)
<daveshah> lt refers to LUT and lc refers to logic cell
<mithro> daveshah: LC is ~LUTFF ?
<daveshah> Yeap
<daveshah> Including the FF bypass
<pb_> gif is routing pairs form wip-report-2.txt, 1:13 white:black
<pb_> and unless i really screwed with aligning of your name scheme, quartus one seems to be more consistent
<rqou> yeah, somehow the quartus names make more sense for horizontal wires
<rqou> i've been trying to find some kind of physical explanation for that
<rqou> starting to think this will require decapping the chip
<rqou> anyways, discovered quite a few missed routes
<rqou> also found a "feature" in the column ios that i can't explain at all
<mithro> daveshah: Does this look right for the neighbourhood tracks? https://usercontent.irccloud-cdn.com/file/RGc7lUtb/image.png
<daveshah> mithro: yeah
<daveshah> Looks good
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<daveshah> mithro: No, sorry, wrong way round I think
<mithro> daveshah: So it kind of works like this for the IO? https://usercontent.irccloud-cdn.com/file/PrQb2pbc/image.png
<daveshah> mithro: follow the connections shown here: http://www.clifford.at/icestorm/bitdocs-1k/tile_8_1.html
<daveshah> The logic_op in IO are for logic to IO
<daveshah> There are no IO to IO neighbours
<daveshah> And I think both those diagrams are the wrong way round, if you check the above
<rqou> wow max v has tons of bullshit features
<rqou> it is entirely unclear how the heck lab control signals work
<rqou> because each one seems to be slightly different
<daveshah> Yeap, that's correct now I think
<mithro> daveshah: That look better?
<mithro> daveshah: It pairs with this, right? https://usercontent.irccloud-cdn.com/file/MulDRDrP/image.png
<daveshah> mithro: Yeah
<daveshah> That looks correct
<mithro> daveshah: Great!
<daveshah> Also note that at the corners, a couple the neighbour outputs that would correspond to non existing tiles in the corners are actually used for outputs from the PLL
<mithro> daveshah: Yeah - I've been pondering the PLLs
<daveshah> Another thing of note is that the RAMs also output onto the neighbour tiles as if they were logic tiles
<daveshah> E.g output 0/8 corresponding to neighbour 0
<daveshah> Same with the DSPs and IP
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<openfpga-github> [Glasgow] awygle pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/6cb4f9972d681bcb62dff08dbc81986b0b11e50b
<openfpga-github> Glasgow/master 6cb4f99 awygle: Minor silkscreen cleanups.
<rqou> wow it's surprisingly difficult to figure out how to activate the logic tile control signals
<rqou> i also can't figure out how to activate global clocks
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<rqou> PSA: You need `set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to a` to force use of global wires
<gruetzkopf> *nods*
<rqou> and yes, you can force a "global" wire that only goes to one place
<rqou> don't do this in production of course
<awygle> Don't Do This In Production - The ##OpenFPGA Chronicles
<rqou> aaaah shit
<awygle> Don't Do This In Production would actually be a great name for a biography. I would be satisfied if my biography was called that.
<rqou> not every mux is the same like i thought
<rqou> wait wut
<rqou> something weird is going on
<rqou> at this point "something weird is going on" should probably be the motto of Project Chibi
<qu1j0t3> awygle: +1
<qu1j0t3> mine can be called Testing in Production
<rqou> hmm how does this work? the normally two-hot muxes become magically a one-hot mux when a global wire is used
<daveshah> Maybe it reduces delay or skew marginally
<daveshah> By only needing one switch stage
<rqou> but how is the silicon built to recognize this?
<awygle> Maybe it skips a layer, yeah. Wasn't there one bit pattern that wasn't used?
<daveshah> So I imagine the two hot multiplexers are two one hot multiplexers cascaded
<daveshah> Except that the final multiplexer has som direct global inputs
<rqou> except that global nets _reuse_ bits that also appear in other patterns
<daveshah> Without going through a first stage
<daveshah> Oh, that's much weirder
<daveshah> So you mean like one of the normal inputs, but with only one bit set?
<rqou> yeah
<daveshah> or cleared, as I think max v is?
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<gruetzkopf> more like "You did what now with WHAT?" for me
<sorear> Maybe what you think is the first stage is actually the second
<gruetzkopf> including a not-quite-yet-working clone of the pokemon gen2 engine to centrifuge controllers.
<pie_> <rqou> and yes, you can force a "global" wire that only goes to one place
<pie_> yay antenna \o/ ?
<gruetzkopf> (well, civil tech that uses the same graphics subsystem)
<pie_> ITAR-ed pokemon games
<rqou> pie_: not a very good antenna since there's buffers in the middle that turn off unused spurs
<rqou> (although i think i know which bits control them)
<pie_> aww
<pie_> gruetzkopf, actually i just realized, how did you even get the software for the video card over laptop pcie thing working? im guessing the pcie stuff is more flexible than i suspect
<gruetzkopf> the "cursed gaming" adapter?
<gruetzkopf> just works
<pie_> ah.
<pie_> i need to move to cccac
<pie_> rqou keeps telling me to move
<pie_> halp
<gruetzkopf> (with the laptop in the video having a firmware bug, which turns off the intel gpu because when there's a nvidia GPU present it's clearly the integrated one)
<rqou> pie_: i mean, HU isn't really the best tech/hacker hub ever :P
<pie_> stahp :(
<pie_> gruetzkopf, almost surprised you didnt fix that too :P
<gruetzkopf> works fine for my normal choice of thinkpads
<pie_> so...is that something you actually use
<pie_> has someone commercialized this yet
<rqou> pie_: w̋i̋t̋h̋ a̋l̋l̋ őf̋ y̋őűr̋ w̋őr̋d̋s̋ l̋őők̋i̋n̋g̋ l̋i̋k̋e̋ t̋h̋i̋s̋ :P
<pie_> though im pretty sure ive heard of stuff like video card over usb or something so i wouldnt be surprised
<rqou> also i really need to get a better "weird unicode" input method
<pie_> just type with a chinese keyboard, westernerns cant tell the difference :p
<rqou> but how do i make fun of hungarian that way? :P
<rqou> oh what
<gruetzkopf> it's commercially availabe, yeah
<gruetzkopf> even more so today than half a year ago
<rqou> pie_: i don't even have fonts for that
<pie_> apparently i dont either
<pie_> shame.
<awygle> that's a cool alphabet
<rqou> oh wtf: "In LaTeX, the double acute accent is typeset with the \H{} (mnemonic for Hungarian) command."
<rqou> why can't latex support unicode like a normal program?
<egg|zzz|egg> meow
<egg|zzz|egg> rqou: use XeLaTeX
<egg|zzz|egg> rqou: and LaTeX doesn't because it's from 1983 and based on TeX which is from 78 :-p
<rqou> it can't get upgraded?
<pie_> rqou, lualatex and xelated do
<pie_> there are ?hacks? for getting latex to work with fancy characters
<pie_> i never really looked into how that shit works
<pie_> seems unnecessarily arcane
<rqou> that describes all of latex though
<pie_> on one hand *latex is pretty cool, on the other hand, good god WHY
<pie_> qu1j0t3 may be able to say otherwie
<pie_> otherwise
<awygle> i like the implication that "normal programs" support unicode
<awygle> it seems to me more an aspiration than a truth though
<rqou> "normal*" *void in US/JP
<pie_> my friends game saves kept getting put in oddly named folders because his windows account name had an accent in it
<pie_> i dont know if it was a windows or a game issue
<rqou> fine then, "normal*" *void on win32, especially in US/JP
<pie_> i should have known better but i spent half a week trying to get a game to run on different machine, for probably the same reasons
<pie_> then it hit me.
<awygle> it annoys me that it's not win64 now
<egg|zzz|egg> rqou: I mean, yes, normal programs written sensibly in the past couple of decades by *are* Unicode-aware
<pie_> "<rqou> nothing is good enough for you people"
<egg|zzz|egg> but those built up from the seventies, less so
<rqou> egg|zzz|egg: except on windows in US/JP? :P
<egg|zzz|egg> I don't know, I'm not in US/JP
<egg|zzz|egg> I do use Windows though, and I'm quite happy with its Unicode support :-p
<pie_> im just glad i was born in a time unicode exists
<pie_> cant imagine the encoding fuckery otherwise ( and yet there is still plenty of encoding fuckery
<rqou> egg|zzz|egg: i consistently learn about new wtfery in windows caused by microsoft digging in their heels with utf-16
<awygle> fuckin' utf-16. worst encoding possible.
<gruetzkopf> stay far away with your surrogate pairs
<egg|zzz|egg> rqou: it's hardly Microsoft-specific, see also Java
<egg|zzz|egg> it made sense at the time when Unicode was going to be the BMP
<egg|zzz|egg> then it eggspanded :-p
<awygle> it's used in a lot of places unfortunately
<awygle> often under the unqualified name "unicode"
<awygle> just to make it worse
<egg|zzz|egg> *that* is annoying
<awygle> yarp
<egg|zzz|egg> meow
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<awygle> apropos of nothing - i came across some code this week that sends a 32-bit value over the network in little endian order, then calls le2hl on the other side. this irritates me, because it implies knowing about network order, and deciding not to use it.
<rqou> lol
<pie_> HEH HEH HEH
<awygle> it's not even using any of the "dump this on the network in native order" tricks. it writes it a byte at a time in LE format. like... why?
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<awygle> hm is bank 3 on the ic40 HX the only one that does differential pairs?
<rqou> wtf
<rqou> one of my fuzzers is broken
<egg|zzz|egg> rqou: use a cat
<rqou> no cat :(
<rqou> maybe awygle's cats can help
<awygle> rqou: the skinny one is helping me make a kicad symbol atm, but you can borrow the fluffy one i suppose
<rqou> lol
<rqou> put photos on birbsite?
<rqou> oh wtf
<rqou> i guess this is what happens if you write fuzzers in a hurry late at night
<sorear> Network byte ordering for the 21st century
<pie_> cat fuzz
<sorear> BE only was a thing for TCP/IP because of 68k dominance
<egg|zzz|egg> awygle: catpics?
<egg|zzz|egg> cats!
<awygle> they are cutie pies
<awygle> i am such a bad photographer lol
<awygle> i re-realize this every time
<qu1j0t3> egg|zzz|egg | rqou: and LaTeX doesn't because it's from 1983 and based on TeX which is from 78 :-p // It was rewritten for "TeX 82"
<egg|zzz|egg> yes
<egg|zzz|egg> but what if you want to use a non-ASCII ISO 646 encoding :-p
<qu1j0t3> well, TeX includes a mapping table so you could probably hack it, but that's an '80s hobby
<egg|zzz|egg> :-p
<egg|zzz|egg> I mean we *are* discussing this over a protocol which has ISO 646 legacy
<qu1j0t3> i'm sure there are like 150 TUGboat articles from European users on such hacks :)
<egg|zzz|egg> try /nick egg\zzz\egg
<rqou> another altera wtf: afaict GCLK0/1 are "better" than GCLK2/3
<pie_> rqou, i like how i atched a couple dragon maid videos and now my entire youtube suggestions is that, but when i listen to some good music my suggestions are full of random crap that just never ever goes away
<rqou> altera's arch is full of tons of _weird_ limitations
<rqou> yeah, youtube's algorithms are _awful_
<rqou> i've complained to my housemate about this many tiles
<rqou> *times
<awygle> i find that youtube's algorithms are the least awful of all the recommendation engines
<rqou> no way
<awygle> but that they get really stuck on certain themes for no good reason
<rqou> i.e. alt-right conspiracy theories?
<awygle> and then there's the whole radicalization thing of course
<rqou> at $WORK i don't have adblock installed, and i use youtube to listen to music
<rqou> most of which is video game soundtracks/OSTs
<awygle> but the front page "here's shit you'd care about" page has always been pretty decent for me
<rqou> and i get the _worst_ ads
<pie_> also using youtube for music is so wasteful, bandwidth pls
<awygle> oh yeah the ads are horrible
<rqou> e.g. blatantly sexist "gamer" crap
<awygle> but all ads are horrible
<pie_> its kind of weird having been around to see "e-sports" take off
<pie_> then again its not like i ever saw a lan party before that so i wouldnt really know
<pie_> maybe its just more visible now
<awygle> there was a time when i for various reasons was watching crunchyroll
<awygle> and they have the _worst_ ads
<awygle> they do like 12 ads per 22-minute episode, and frequently it was _the same ad multiple times_
<awygle> plus there was this one that was for a snack bar of some sort that still haunts my dreams because it just made _no fucking sense_
<pie_> awygle, i guess that was the point
<awygle> but apparently it didn't bother anybody else because searching for "it shows off your long giraffe neck" yields basically no results
<awygle> pie_: well, yes, but i can't name the company it was an ad for :p
<pie_> lmao
<pie_> maybe you hallucinated it after the nth horrible ad
<pie_> your mind just broke and said "i can do better"
<awygle> do "BGA", "LFBGA", "TFBGA", "DSBGA", "UFBGA", and "VFBGA" have actual meanings? or are they just marketing things?
<awygle> like are all TFBGAs 0.8mm pitch or something?
<rqou> hmm, pretty sure LAB_CLK is a dummy route that doesn't do anything
<rqou> since they use that term even for IO tiles that aren't LAB tiles
<pie_> maybe they are all the same thing and naming is arbirtrary? :D
<awygle> Problem: Naming things is hard. Solution: Only have one thing!
<qu1j0t3> WUXGA
<rqou> lol qu1j0t3
<pie_> awygle, name the same thing multiple things
<rqou> stahp
<pie_> internals arent user facing anyway!
<rqou> pie_ i'm already having enough trouble with this already, stahp
<rqou> also, i love how i can route pin->global net->pin
<rqou> 0 luts
<rqou> most efficient use of resources ever
<awygle> lol
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<pie_> rqou, IM SORRY THIS IS A FACEBOOK LINK BUT OH MY GOD https://www.facebook.com/GameSpot/videos/10160792147255436/?__fns&hash=Ac3_dH4sDVpkf3WM
<rqou> sorry, something went wrong :P
<pie_> ugh
<pie_> cant even direct link the shitty video
<rqou> it's interesting how the docs for routing constraints recommends you don't mess with global signals
<rqou> because (at least in this chip) they're really simple and obvious how they work
<rqou> wat
<rqou> l/r ios aren't symmetric
* pie_ never actually played COD so no hype on that part
<rqou> wtf
<rqou> that looks pretty amusing
<pie_> thought it was kanna in the beginning but its not
<rqou> pie_: i hope you're going to be happy when/if project ravioli gets started :P
<pie_> ravioli ravioli headshot by the dragon loli?
<rqou> lolol
<pie_> i will be amused
<pie_> if i ever get into software dev all my flagship products are going to have anime girls
<pie_> i mean as mascots
* pie_ starts pondering anime girl clippy replacements
<pie_> HMMMMM
<rqou> fpga-tan :P
<pie_> its genius!
* qu1j0t3 saves this and taunts 43 year old pie_ later
<pie_> just so i can alienate anyone that takes themselves at all seriously otherwise dislikes japanese stuff
<pie_> *or otherwise
<pie_> rqou, this is what we need to get open source fpga off the ground
<pie_> qu1j0t3, this neets to be archived for posterity so that people can look back and say yes, these are the men that got us where we are today
<qu1j0t3> and women
<pie_> qu1j0t3, well i mean im a dude
<pie_> but yeah i guess there was a lot implicit in that phrase
<rqou> wat, the column ios now have _more_ connections to the global wires
<pie_> today on rqou builds the singularity: "Im confused. Why does this work at all?"
<awygle> The worst feeling in sw dev is "oh awesome I found the bug!.... Wait, this should never have worked!"
<cr1901_modern> Your Best Girl won't love you back, pie_ :(
<cr1901_modern> Or mine, for that matter
<rqou> ok in the columns this feeds into the "normal" mux
<pie_> cr1901_modern, oh no :(
<cr1901_modern> Or anyone's, really...
<pie_> cr1901_modern, im not 100% sure how we jumped to this
<cr1901_modern> >if i ever get into software dev all my flagship products are going to have anime girls
<pie_> ah ok yeah i follow, i thikn
* pie_ is the one meanwhile writing scifi...I might get a bit closer :c
<pie_> *attempting to write
<rqou> oh LAB_CLK is just the buffer in the middle of the column
<rqou> it's just named weird
<pie_> <rqou> it's just named weird
<pie_> semantic gaaaap
<awygle> semantic gap moe
<awygle> (that sounds like a wheel of fortune puzzle)
<pie_> "Moe characters have expanded through Japanese media, and have contributed positively to the Japanese economy"
<pie_> " have contributed positively to the Japanese economy"
<pie_> they wake up, go to work, etc
* pie_ had to look moe up because he never quite figured out what it meant
<awygle> specifically a Before & After puzzle
<awygle> pie_: that's okay, I had to google semantic gap :-P
<pie_> awygle, i originally googled it because it sounded like somethng someone would have come up with already xD
<pie_> still kind of wish it could be my thing :( :p
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<gruetzkopf> so i have this set of PBXes that's hard to connect to the modern world because germany essentially skipped a step in telco systems most other locations did
<gruetzkopf> i don't want to build my own E1 card :(
<gruetzkopf> (germany essentially jumped from a rotary dial system designed in 1955 directly to CCS ISDN, with *very* few exceptions)
<rqou> so, anybody feel like doing some project chibi work on bits that are much further out ahead?
<rqou> it'd be nice if somebody could poke at how the JTAG USER0/USER1 functionality works
<rqou> since this seems to be completely undocumented
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<awygle> .... do lattice's BGA recommendations look to anyone else like they got SMD and NSMD mixed up?
<rqou> no?
<awygle> hm actually it seems inconsistent
<awygle> like the 121 caBGA seems backwards, but the 36..225 ucBGAs seem correct
<rqou> hrm
<rqou> poke azonenberg?
<rqou> also, i've never used SMD
<awygle> actually this makes even less sense. i must be interpreting this wrong.
<awygle> the dimensions for the ucBGA would make both the SMD and NSMD dimensions SMD
<rqou> the SMD number is the solder mask opening
<rqou> the NSMD number is the pad size
<awygle> oh, that's better
<rqou> which is surprisingly small actually?
<awygle> but in that case they don't specify the expansion for NSMD or the pad size for SMD?
<rqou> lol apparently not?
<awygle> ohhhhhh i figured it out. the first two columns are what's on the _part_, not what you should put on the _board_
<rqou> yes, that too
<awygle> the _part_ has SMD pads, but you can do whatever you want
<rqou> awygle is very good engineer :P
<awygle> i figured it out before i hit fab :p
<pie_> <awygle> .... do lattice's BGA recommendations look to anyone else like they got SMD and NSMD mixed up?
<pie_> didnt someone at some point mention something about an acronym messed up in one of the menu items?
* pie_ catches up on scroll