<cr1901_modern> Oh, it's the Adapteva person...
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<rqou> azonenberg: this is interesting
<rqou> io bits corresponding to pads that clearly don't exist are blank
<azonenberg> interesting?
<rqou> but the one unbonded pad aren't
<rqou> *the ones corresponding to
<rqou> so the other day i mentioned there was a "pad view" as opposed to the normal "pin view"
<rqou> the "pad view" shows there's an unbonded pad at the top left
<rqou> and the top left has the full set of bits
<rqou> so it really does exist
<rqou> we just can't access it
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<rqou> azonenberg: the left and right IOs are way more asymmetrical than i thought
<azonenberg> oh?
<rqou> yeah, the input delay bits are not mirrored, and shifted by 1
<rqou> actually no, they're just in totally different places
<rqou> O_o
<rqou> azonenberg: the top/bottom local interconnect muxes are also not the same as the normal muxes
<rqou> the normal muxes have 13 settings, right?
<rqou> these ones stole one of the settings and reused the bit to control the io delay
<azonenberg> lol
<azonenberg> sounds like you still dont quite have it figured out?
<rqou> i believe i do
<rqou> but i can't confirm that there are no more secrets
<rqou> i mean, in general this style of fuzzing can't confirm that, can it :P
<azonenberg> well yeah
<rqou> hey azonenberg, random speculation time
<rqou> azonenberg: what do you think this bit controls? https://i.imgur.com/mdlSMkC.png
<azonenberg> Can't begin to guess
<rqou> the weird thing i'm noticing is that it's outside the boundaries of any "normal" structure
<rqou> azonenberg: so e.g. right below it is a left-side io, to the right is a top io
<rqou> so wtf is hiding in the corner like that?
<azonenberg> probably some kind of global config?
<rqou> like what?
<rqou> the two i looked at are at the bottom-left near the usercode
<rqou> there's a global output enable there and a global clear signal there
<azonenberg> idk
<azonenberg> just thinking
<azonenberg> xilinx cplds use the middle of the ring-shaped logic blocks for global config
<azonenberg> but fpgas tend to us ecorners outside the fabric
<rqou> maybe it controls the flash memory block?
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<azonenberg> Could be?
<azonenberg> reboot retry count or something?
<rqou> no, as in enabling various functions in that block
<rqou> e.g. the internal oscillator
<azonenberg> maybe
<azonenberg> something akin to the register writes in a xilinx .bit prior to the actual FDRI write?
<rqou> wut?
<azonenberg> you know how a xilinx bitstream is constructed at a high level right?
<azonenberg> (for fpga, not cpld)
<rqou> i know there's a big weird FSM
<rqou> er, back up
<rqou> there's the .bit container
<rqou> and inside it is a microcode for some FSM
<azonenberg> i'm talking about the next layer down
<rqou> and then inside that is "frames"
<azonenberg> that
<azonenberg> I wouldn't call it microcode
<azonenberg> it's a canned list of {register, value} tuples
<rqou> yeah, this isn't anything like that at all
<azonenberg> One of those registers is "frame data register in" or FDRI
<rqou> it's just a dump of flash contents afaict
<azonenberg> Which is where the actual config frames go
<rqou> as in the .svf just shifts this data in 16 bits at a time
<azonenberg> This is the actual format the chip interprets
<azonenberg> only the .bit container is for tools to use
<rqou> afaict in this chip there's the .pof container for tools
<azonenberg> anyway, my point is that altera might just use "position in the bitstream" to denote register ID
<rqou> and then the actual data is just 0xD000 bits
<azonenberg> rather than having it be explicit like xilinx
<rqou> well, some parts of it are special
<azonenberg> But there may still be configuration-type stuff in there
<rqou> every 32 bits has 3 "weird" bits
<rqou> that i've rearranged to the bottom
<rqou> one of those is always 0, forming those horizontal stripes
<rqou> and then padring settings are shoved in between
<rqou> there are some settings about what to do with pins during a reflash operation
<rqou> but they don't appear in this 0xD000 bits
<rqou> they appear as a flag in the .pof (that i don't care about)
<rqou> and just end up using a different set of jtag commands
<rqou> so afaict there's no "registers"
<azonenberg> well there are, they just don't have any kind of address map :p
<azonenberg> its closer to how coolrunner does it
<rqou> yeah
<azonenberg> this bitstream pos = setting X
<rqou> pretty much
<rqou> so my guess is that that bit controls the UFM somehow
<rqou> oh btw azonenberg, hilarious (documented) "feature"
<rqou> this chip supports flashing the flash memory without disturbing the running design...
<rqou> but it warns you that if you try to access the UFM while this is happening, you will corrupt it
<rqou> so the UFM has a "warning, i'm about to perform reflashing" wire
<rqou> and it's the user code's responsibility to check that and then stop issuing requests against the UFM
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<daveshah> Xilinx RFSoC devkit is now available, just $8995, if anyone wants a new RE challenge...
<daveshah> fpga is €16k, not actually bad given the ADCs and DACs alone wouldn't be super cheap
<rqou> nah, don't have that kind of cash
<rqou> if i were to do something of that scale i'd probably work on Project Lucoa (hey, blame pie_) targeting the arria in the g-sync monitors
<rqou> btw azonenberg, any objections to that name? :P
<pie_> here be dragons :O
* pie_ goes back to grinding haskell
<pie_> tbh its more like coding python though because of imperative bindings...
<pie_> except minus the mindfuck runtime errors
<pie_> (ok now you have to figure out whats going wrong at compile time but its not too bad so far)
<rqou> pie_: should try rust :P
<pie_> yeah
<pie_> i want to make a $$$ ymbol but for time
<pie_> *symbol
<rqou> ⏰⏰⏰
<rqou> also, azonenberg you should try rust
<rqou> don't you like not having memory safety errors?
<pie_> ;3
<rqou> and you get a nice powerful (but still reasonable) type system too
<pie_> well until you shoot yourself in the foot with something weird but it cant be WORSE right? :p
<rqou> it's designed to be practical, not for PL wankery
<rqou> unlike haskell :P
<pie_> except its better >> percent of the time
<pie_> ^ not @ haskell
<azonenberg> rqou: lolol
<azonenberg> thats an interesting feature :p
<azonenberg> coolrunner has the same capability, but is not user writable
<azonenberg> since there's no extra bytes available
<rqou> um, ime sram programming doesn't actually work
<rqou> oh wait, it can _also_ do the same thing as altera
<rqou> and afaict that does actually work
<rqou> but yeah, max v has a pretty neat 8192 bits available for user storage
<rqou> azonenberg: btw, why do you hate Rust?
<azonenberg> i hate rewriting existing projects in rust bc you dont like c++ :p
<azonenberg> i need to learn rustm planning to play with it for antikernel
<rqou> why don't you play with it sooner and convert to the dark side? :P
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<cr1901_modern> >just $8995
<cr1901_modern> Sure, I'll take twenty. Does Xilinx accept organs as payment?
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<awygle> rqou: corner bit some kind of clock buffer enable?
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<rqou> damn awygle you get up early
<rqou> and no, those are in the middle
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<rqou> wtf?
<rqou> OFTC just banned me?
<sorear> Probably just one channel?
<rqou> "autokilled: Possible spambot."
<rqou> great
<rqou> IR time
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<sorear> Killed isn’t a ban, can you rejoin?
<rqou> huh, apparently i can now
<rqou> i guess they were just doing weird maintenance?
<rqou> earlier it was actually reporting "Banned"
<sorear> Some weird shit was going on
<sorear> #oftc blamed skiddies
<rqou> ah ok
<rqou> i was a little bit concerned because my server has some "fun" configurations that potentially could allow an attacker to get access to IRC
<rqou> i run ZNC as a proxy for my crappy scripts to connect to IRC without having to deal with all of the difficulties of actually connecting to IRC like authenticating and reconnecting
<rqou> this interface is bound to an internal IP but isn't authenticated
<rqou> it's firewalled off so that only containers on the same server can use it
<rqou> but one of the containers is the perpetual CVE magnet, jenkins
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<awygle> rqou: I mean, 8am. Not that early.
<awygle> I suggested clock buffers because some arches have like "quadrant" clock networks
<rqou> yeah, those are also in the middle
<awygle> but I guess that makes little sense on the chibiest fpga
<rqou> it's per-column buffers in this case
<rqou> it's actually quite obvious that they're there
<rqou> "oh, i wonder what this one single row of bits controls? it's right in the middle, and every column has four bits, and there are 4 gclk wires"
<awygle> Lol
<rqou> although there is a trap
<rqou> the first column of ios has enables too, but it doesn't have enough room for these bits
<rqou> so these bits are shoved into the next column on the right
* awygle has no food in the house
<awygle> time for shopping
<rqou> <insert that weird birbsite/weeb mcdonald's meme here>
<awygle> ...?
<rqou> if you missed it, i'm not going to bother to dig through and try to find it
<awygle> fair enough
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<rqou> hmm, why does max v io have a dedicated open drain mode?
<rqou> ah, it allows use of the fast path
<daveshah> yeah, that is quite common in fpgas
<rqou> huh, open-drain mode is configured in the "padring" bits
<rqou> not the fabric bits
<daveshah> Yeah, it's the same for the ecp5
<daveshah> It seems that output enable for the ecp5, OTOH, is two bits on the fabric/IOLOGIC side
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<rqou> azonenberg: have you ever considered mechanical delayering like this? https://twitter.com/marcan42/status/1013158454171656192
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<pie_> rqou, whuuut
<pie_> how the hell do you delayer with a razor
<pie_> i find it amusing / scary how you guys can recognize IP by looking at pictures but i understand how you would learn to do that :p
<pie_> rqou, ahh i forgot about this post https://twitter.com/marcan42/status/919682733621829632 i feel like i impinged upon marcan 's territory
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<rqou> <drama>wtf is iota and why the heck do people even care about it? why so much drama/making fun of them?</drama>
<Ultrasauce> my understanding is it has fundamentally bad crypto and lots of shills
<Ultrasauce> a winning combination
<rqou> but that's neither unique nor particularly interesting?
<Ultrasauce> perhaps those are not criteria that matter to infosec twitter
<rqou> alright, whee, time to figure out how to use the UFM/JTAG primitives
<rqou> the IOs weren't actually that complicated after all
<rqou> wut
<rqou> the internal jtag primitive has ports that can't actually be used
<rqou> undocumented primitives are "fun"
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<rqou> hmm, the UFM may have an undocumented wire too
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<rqou> hrm, something doesn't add up still
<rqou> there's not enough wires for the UFM to "squeeze in" the same way the JTAG is squeezed in
<mithro> Afternoon everyone