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<azonenberg> rqou: whats weird about my schematic?
<rqou> it's labeled with io bank numbers, not fb numbers
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<azonenberg> kc8apf: yes, but it doesnt give any detail into how the DNA is calculated
<azonenberg> rqou: well duh
<rqou> and on XC2C32A these just so happen to be opposites
<rqou> why duh?
<azonenberg> thats always the case, i dont assume knowledge of internal architecture when doing the sch
<azonenberg> that trend continues to all larger devices
<azonenberg> kc8apf: conjecture: DNA {wafer lot, die x coord, die y coord} or something thereabouts
<azonenberg> rqou: you just got unlucky with the 32a because they're opposites
<azonenberg> (which imo is stupid, why did they not make them the same?)
<rqou> and then mirroring the bitstream really does mirror the functionality :P
<rqou> for extra confusion
<azonenberg> lol
<rqou> and the programmer qualification doc is super confusing regarding bit order
<rqou> I'm amazed you didn't also manage to do this
<sorear> I think dna has to be fused, I don’t think it’s possible to program in coordinates if you’re using a stepper
<azonenberg> sorear: yes its definitely fused
<azonenberg> But that doesnt tell you what they put in the fuse
<sorear> I would hope a random number, but too many people are unfamiliar with the German tank problem
<azonenberg> well stmicro actually tells you whats in their serial
<azonenberg> its an ascii wafer lot ID (which doesnt tell you how many lots they do, its probably the TSMC or whatever internal lot #)
<azonenberg> followed by packed binary X/Y
<azonenberg> the datasheet even describes the bitfields
<azonenberg> for stm32
<rqou> rant: when are the homebrew devs going to stop 420-ing and give everything a sane name?
<pie_> turn around 420 degrees and walk away
<mithro> Does anyone here know about the routing muxes in the ice40?
<rqou> obviously, they exist
<rqou> routing muxes are indeed a feature of the ice40
<mithro> In the icebox DB there seem to be different bits which are need for (6, 4) ('routing', 'sp4_v_t_47', 'sp4_v_b_10') verse (6, 4) ('routing', 'sp4_v_b_10', 'sp4_v_t_47')
<mithro> Do I need to "enable" both the ('routing', a, b) and ('routing', b, a) entries? or?
<mithro> I'm guessing daveshah is asleep :-P
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<kc8apf> I may have gone a bit overboard with this debugging tool: https://gist.github.com/kc8apf/3493b88a640bf31fb1fe4f07f7bb6487
<pie_> kc8apf, run length encoding? :P
<pie_> or like, [snip] lots of identical line
<kc8apf> you want more complexity???
<pie_> of course \o/
<pie_> you cant stop until you need to debug the debugger
<Bike> well if it's a choice of complexity or twenty thousand lines of zero
<kc8apf> I just wish packed_struct used lsb0 bit numbering....
<rqou> ugh i keep finding that xc2par blows up on really straightforward designs but seems to accept incredibly complicated ones
<rqou> classic rqou problem
<qu1j0t3> :)
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<rqou> azonenberg: hmm, so what do you make of this? every LUT bit in max v is towards the "end" of a group of bits controlling a column
<rqou> probably means i need to read vertically?
<azonenberg> Probably
<azonenberg> the luts are prob stretched out
<azonenberg> most luts are dff+mux structure
<azonenberg> not normal sram addressing
<rqou> also, afaict the data has two "halves"
<rqou> but they seem to be of different sizes
<rqou> see the two black columns?
<rqou> the left hand group has 32 columns between the black columns
<rqou> the right hand group has only 30
<azonenberg> global clocking in one or something?
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<rqou> i don't think so?
<rqou> so, in that visualization, each "messy-looking horizontal line" seems to be where the column boundaries are
<rqou> except i'm not sure what's going on with io columns
<rqou> there's a big block of stuff at the end
<rqou> there are clearly patterns in how the lut bits are arranged, but it's not super obvious
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<rqou> azonenberg: whelp, i wrote a tool to automatically mark things, and now it's totally obvious which columns are special :P
<azonenberg> :)
<rqou> also, most of the control bits are definitely routing
<rqou> screw it though, i might just fuzz an entire column at once
<azonenberg> Not surprisedi n the slightest
<azonenberg> They're one hot i take it?
<azonenberg> (this tends to bulk things up a lot)
<rqou> an entire column is 7168 bits
<rqou> i don't know anything about the routing at this point
<rqou> i just have luts
<azonenberg> and you're using the standard fuzzing methodology for now?
<azonenberg> constrain a lut, synth it, see where the bits show up?
<rqou> yes
<rqou> i'm going to switch gears to routing though
<rqou> since lut bits are honestly boring :P
<azonenberg> well i mean its usually obvious what a lut is
<azonenberg> the only question is which bit is where
<rqou> fortunately, both the thing we discussed privately as well as random forum posts on the intertubes tell you exactly how to constrain routing
<rqou> so the only thing you don't know is *) what are you allowed to constrain it to *) what bits control that
<azonenberg> Makes sense
<daveshah> Can you not find an API for the first one?
<daveshah> I found one semi hidden inside Diamond
<rqou> i looked and couldn't find one
<rqou> it seems they went through some effort to hide it
<rqou> er well, there is one
<rqou> interactively
<rqou> i haven't found a scriptable one
<daveshah> In Diamond it was actually in a "legacy" (I think) TCL console that you could start separately
<azonenberg> awygle: almost done redoing the line card to fix the screwed up routing
<azonenberg> from the pinout derps
<rqou> hey azonenberg, how's the house btw
<azonenberg> rqou: We got the fireplace out of the dumpster the other day, havent had it disposed of yet thoguh
<azonenberg> the insert i mean
<azonenberg> the big fireplace is gone now
<rqou> did the redneck take it?
<azonenberg> Yeah
<azonenberg> he said he'd be back for the other piece
<azonenberg> I still have his beer, so if he wants it he'd better grab it :p
<azonenberg> Got a late start today because we had somebody over the rental house doing repairs that we had to be home for
<azonenberg> Spent the rest of the evening fishing wires through sketchy places in the ceiling
<azonenberg> pulling conduit and hooking up power to the office lights and wall outlets
<azonenberg> (we had the outlets done but there was no power feed to any of them)
<azonenberg> Tomorrow after work the plan is to finish the remainder of the feeds to the office, pull one more data conduit in the office, then a few hookups we didn't get around to in the garage yet
<azonenberg> And probably the hallway light downstairs, we have the light box but no switch or power yet
<rqou> when's inspection?
<azonenberg> We just have to give them a day or two's notice
<azonenberg> so not scheduled yet
<rqou> wow, that fast?
<azonenberg> original goal was end of the month, but the fireplace delayed it
<azonenberg> So i'm slipping to end of the weekend
<azonenberg> Saturday will be wiring up the laundry room (just 2-3 outlets on the gutted wall, we're keeping most of the rest of the room intact)
<azonenberg> and then risers from the cable trays to the second floor circuits
<azonenberg> Sunday is miscellaneous catch-up
<azonenberg> Then we'll be spending next week doing cleanup, spraying vinegar and mold killer everywhere
<azonenberg> and doing little tidbits of framing needed for sheetrock prep
<azonenberg> while we wait for the electrical inspection itself
<azonenberg> once it's signed off we can do the city inspections for framing, plumbing, and hvac
<azonenberg> By the time that's done insulation should be here and we can install that middle of the month
<azonenberg> Inspect that, then spend the last week of the month hanging sheetrock
<gruetzkopf> oh, low-current-low-voltage wiring :D
<azonenberg> If we have downtime waiting for stuff to happen i plan to order the sheetrock early
<azonenberg> and start measuring/cutting it
<azonenberg> Even if we're not ready to close the walls, having premeasured/precut panels staged will make the hanging quick once we get permission to do it
<azonenberg> Such that the actual hanging can be done in a couple of days
<gruetzkopf> i've installed a temporary 400V 32A 3ph circuit yesterday so i i can have warm showers until i can get the spare part for the 58 year old gas heater)
<azonenberg> Lol i see
<azonenberg> yeah we're doing 120V 20A circuits
<azonenberg> but a lot of them
<azonenberg> I have 24 circuits in my notes right now and that's just the new ones i've installed
<gruetzkopf> yeah most circuits here are 230V 16A
<azonenberg> i'm keeping a couple of the 240V circuits for the laundry/furnace and kitchen for now
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<gruetzkopf> in another location i've filled a panel with around 40 of those and live-and-neutral switching breakers
<azonenberg> Then right now the kitchen is still on legacy wiring and the bathrooms have no power at all
<azonenberg> So fixing that is sat/sun's job
<azonenberg> the kitchen is saved for very last though b/c we are using the fridge and microwave to snack during construction
<azonenberg> So when i cut power to that circuit, i need to be ready to re-connect it immediately
<azonenberg> And once i've energized any of my new work, i need to call for inspection within 24 hours
<gruetzkopf> i have 5 normal and a 25A 3ph circuit for the kitchen alone
<gruetzkopf> over here you only need a qualified person to do or check it
<azonenberg> Around here, you need to be a licensed electrician to advertise or take money for electrical work
<gruetzkopf> and that list is pretty broad, and covers nearly all EE degrees ;)
<azonenberg> An unlicensed person can work on their own property, or do work for a friend as long as money doesn't change hands
<azonenberg> Regardless of who does the work it has to be approved by a state inspector
<gruetzkopf> even "long time work in the field" without any specialised electrical training can qualify you
<azonenberg> Yeah there's some grandfather clauses like that to get a license
<azonenberg> in general getting a licensed requires being apprenticed under a licensed electrician for X amount of time
<azonenberg> But again, that only qualifies to you do electrical work for hire
<azonenberg> And you still have to get it inspected
<azonenberg> Re kitchens the minimum requirement here is that you have two "small appliance branch circuits" to the kitchen/dining room area
<gruetzkopf> over here you're supposed to have it done by an electrician listed by the supplier
<azonenberg> 120V 20A dedicated and not routed anywhere else
<azonenberg> for running microwaves, coffee pots, etc
<azonenberg> The kitchen has two existing circuits that i'll be disconnecting and reconnecting since i'm converting all of the old romex to armored cable
<azonenberg> But i'm not renovating the kitchen yet so i'm not touching the existing stuff
<gruetzkopf> on both locations i did major work i've gotten around it
<azonenberg> Then the dining room has its own dedicated circuit
<gruetzkopf> one is on a legacy supply contract which doesn't include that reference
<azonenberg> Then there's dedicated 240V existing circuits to the oven and dishwasher
<gruetzkopf> and the other is not directly connected to the public power distribution network
<azonenberg> You remind me i still have to do the conduit in the garage for hooking power up to my UPS subpanel
<azonenberg> i'm probably going to temporarily wire the UPS panel to unfiltered mains just so all those outlets are live
<gruetzkopf> our kitchen: 3ph/25A for oven and stove, 2*16A for the outlets next to it, spare 16A 3ph (only wired) for a under-table water heater heater, 1*16A for ventilation (prewired), 1*16 for the gas heater (a different one from the broken one), 1*16A for general outlets
<azonenberg> then buy the UPS in a few months when i have some cash :p
<gruetzkopf> do you need to hardwire it or would it be legal for you to add some big CEE connector for in/our and simply plug in a jumper cable
<azonenberg> The UPS plugs into a 240V 30A outlet
<gruetzkopf> my lab is plugged into a 3ph 32A socket
<azonenberg> The output is going to be hard wired eventually
<azonenberg> But short term i'm probably going to run some kind of conduit jumper between the boxes
<gruetzkopf> the ups feed is pulled out and in via 16A 3ph CEE
<gruetzkopf> (three modified smartUPS3000 so they run with 120° phase difference)
<azonenberg> Fancy
<azonenberg> My UPS is eventually going to feed a subpanel with 8 120V 20A circuits coming out of it
<azonenberg> obviously i cant max them all out at once
<azonenberg> Each of the 4 outer walls of the lab, plus each side of the center wall, gets a UPS'd circuit plus a non-UPS'd circuit
<azonenberg> Then the office gets two walls wired with UPS power and two with non UPS
<sorear> How do you tell which outlet is which? Color coding?
<gruetzkopf> me: yep
<azonenberg> Yes, all UPS'd circuits will have red cover plates
<gruetzkopf> here i have normal and green faceplates
<azonenberg> all outlets in lab spaces will also be labeled with the circuit number
<gruetzkopf> at another location i have red ones additionally, for diesel backup
<azonenberg> wife says thats not allowed in the house though :P
<azonenberg> i have no dedicated generator circuits
<azonenberg> The entire panel has a generator transfer switch
<azonenberg> then i just flip breakers on and off to run them on generator
<gruetzkopf> that location does generator switching automatically
<azonenberg> Once i'm settled in i plan to make a checklist of circuits that should be kept on when the generator is running
<azonenberg> basically the UPS inlet, overhead LED lighting, sump pump, and refrigerator
<zkms> in hospitals they do the same, the outlets that are on the UPS / generators are red (but the faceplates are normal coloured, it's just the actual plastic of the outlets that are red because often they put UPS'd outlets and normal ones in the same cover plate)
<azonenberg> yeah i was going to do that
<azonenberg> but red outlets are almost always hospital grade
<azonenberg> Which is expensive
<azonenberg> like $20 per receptacle o_O
<azonenberg> Red faceplates are super cheap on amazon and can be used with standard receptacles
<azonenberg> So i changed my plan
<azonenberg> Additionally, just for ease of wiring the two circuits
<azonenberg> in the lab I'm putting all of the data and non-UPS'd power 4ft above floor level and all of the UPS'd power 1ft above
<azonenberg> the thinking is that ovens, soldering irons, etc tend to have short cords
<azonenberg> and i dont need backup power for them
<azonenberg> so with a ~3ft high bench i'm in about the right place
<zkms> 1ft above floor level seems it'd be non-convenient to reach though :\
<azonenberg> zkms: well thats pretty standard level for outlets
<azonenberg> everywhere in the house is getting outlets 1ft above floor level
<azonenberg> in the lab, i have UPS'd outlets every two studs (32")
<azonenberg> then only a handful of non-UPS'd for heating elements and other noncritical stuff
<azonenberg> In the lab yes, they're below the bench height
<azonenberg> but most of the time i'd be using them to plug in computers, test equipment, etc that's essentially permanently plugged in
<azonenberg> Many of my benches have additional power strips built into the bench itself that will bring some of them up to a more convenient height for plugging in a laptop or other short-term item
<azonenberg> The data boxes are going higher because i expect to be using them to plug into whatever i'm working with on that bench
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<openfpga-github> openfpga/master f952d28 Robert Ou: xc2par: Fix actually using the direct-path register
<openfpga-github> openfpga/master fef56d1 Robert Ou: xc2par: Fix the same bug for registered input buffers
<openfpga-github> openfpga/master 3495ad7 Robert Ou: xc2par: Fix bug where sometimes input graph generation would panic...
<openfpga-github> [openfpga] rqou pushed 3 new commits to master: https://git.io/vhcQz
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<mithro> daveshah: do you know much about the io performance on the UP5K?
<daveshah> mithro: no, I've only looked at internal performance
<daveshah> IO performance is documented in the datasheet
<mithro> There of course a difference between io performance and how fast you can feed the io from the fabric as well I guess
<daveshah> mithro: yes, fabric will be the limit
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<daveshah> claimed max input performance is 250MHz, and output performance form 70-250MHz depending on VccIO
<daveshah> but in reality pushing the fabric beyond 40-50MHz (=80-100Mbps with DDR) is difficult
<mithro> But first thing normally is to convert to parallel - so 250MHz / 10 = 25MHz
<daveshah> mithro: the ice40 doesn't have any kind of SERDES, so already you hit fabric limits just doing that
<daveshah> with clever manual placement a bit better might be doable though
<whitequark> daveshah: have you ever used SB_IO registers?
<daveshah> whitequark: only for DDR IO
<whitequark> ah ok
<whitequark> I tried and found the timing benefit at best marginal
<daveshah> mithro: let's say maybe 100-120Mbps/pin max, so 200-240Mbps max for a 2-lane link
<whitequark> daveshah: is there any chance I could convince you to throw a very incomplete timing analyzer for arachne-pnr
<whitequark> I'm willing to draw the rest of the owl but I don't want to figure out how to fit it into arachne
<whitequark> I'm consistently bumping into arachne-pnr's limits
<daveshah> whitequark: i can't discuss anything further in public
<mithro> whitequark: What type of designs?
<whitequark> mithro: I get some really odd issues driving the FX2 FIFO on UP5K
<whitequark> I had to rearrange combinatorial circuits around because of what I think is a setup/hold violation
<whitequark> I haven't properly recorded the traces because I don't have anything wide enough to capture the entire bus or even only the important signals, 4ch rigol is the best I have
<whitequark> mithro: maybe if you have an UP5K devboard and an FX2LP devboard you can deadbug this design and measure it, I assume you have a fast LA
<whitequark> I can send you both devboards actually
<mithro> whitequark: I'm afraid I don't actually have time to *do* things -- but I am hitting vpr with a stick
<whitequark> I thought vpr kind of sucks
<mithro> whitequark: Like all software it does -- but a lot less than writing something from scratch
<whitequark> I mean sucks more than arachne
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<mithro> daveshah: BTW Did you see this -> https://github.com/sergicuen/collection-iPxs ?
<mithro> whitequark: I definitely disagree with that
<daveshah> mithro: yeah, a very neat collection of things
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<benreynwar> whitequark: I've looked at both arachne-pnr and vpr in the last month, not having had any exposure to either or to icestorm before. The VPR code base is easier to follow, and more general. It has a bunch of stuff mixed in that's targeting people designing FPGA architectures that makes things unnecessarily complicated but it's not so bad.
<mithro> benreynwar: Sorry I haven't merged your pull request yet
<mithro> tinyfpga: You really need a better website :-P
<mithro> tinyfpga: It's very hard for me to link people to your TinyFPGA BX board explicitly...
<tinyfpga> mithro: they can go to the Crowd Supply Page for now
<benreynwar> mithro: No worries.
<mithro> benreynwar: I have more things for you to do if you want more things :-P
<benreynwar> mithro: Ha! Right now I'm at work (I should really get off IRC), but if you throw something my way I'll have a look this weekend. Ideally fixing something that's limiting in VPR, since I'd like to get into the guts of VPR a bit more.
<mithro> benreynwar: Maybe something like https://github.com/mithro/vtr-verilog-to-routing/issues/4 ?
<balrog> it seems the biggest complaint about VPR is really about ABC
<mithro> balrog: Oh?
<balrog> (with the source of that being that ABC is inscrutable)
<mithro> balrog: And untested...
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<mithro> This looks pretty cool -> https://github.com/cyrus-and/gdb-dashboard
<lain> ooo
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<rqou> wtf
<rqou> azonenberg: ping
<rqou> so I'm using ISE for Coolrunner-II for <REASONS>
<rqou> and I'm trying its "exhaustive fit" option
<rqou> it's implemented the hilarious way that i didn't expect they would do
<rqou> it's literally: for pterms-per-macrocell in <range>: for inputs-per-macrocell in <range>: see if it works now
<lain> lool
<kc8apf> rqou: they mention that in the ISE CLI tools docs
<kc8apf> you can choose how many to run in parallel too
<azonenberg_work> That does sound like an exhaustive search
<azonenberg_work> There's a reason nobody uses that option
<rqou> also it seems like it does go back and forth to synthesize vs fitting
<azonenberg_work> what do you mean?
<rqou> if we were to do it we would have to repeatedly invoke yosys/abc
<azonenberg_work> so you're saying the exaustive option is xst -> cpldfit in a loop?
<rqou> yeah, something like that
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<kc8apf> should all be happening inside cpldfit
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<rqou> also, this might be the first time I've blown the logic limit rather than the state bit limit
<rqou> i suppose that's what happens if you know you'll be state-bit-limited and code the design to minimize state bits
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