ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
<Foone_>
oh yeah, that's the malinov design. TubeTube's design is based on that one, I believe.
<Foone_>
in that he took that design and modified it to more closely match the original adlib design, instead of just being a sort of generic OPL2 soundcard in the same sort of class as an adlib
<ej5>
yeah i started with sergey's schematic but noticed that it didn't match the original in a couple of different ways
<whitequark>
i was wondering who TubeTube is
<ej5>
<--- @tubetimeus on twitter
<ej5>
<--- tubetube in foone's funny little head ;)
<whitequark>
lol
<cr1901_modern>
Malinov has released enough cards such that you can make a 8088-class system where none of the components existed in the 80s :P
<whitequark>
that would be fun
<cr1901_modern>
https://github.com/skiselev/isa8_backplane You can even design your own CPU (on FPGA) to go w/ his ISA backplane, and you get a wide assortment of obsolete-but-still-fun-to-use peripherals
<whitequark>
cr1901_modern: hey you know what would be a fun project?
<whitequark>
an ISA-to-Glasgow adapter
<whitequark>
well
<Foone_>
you mean to use an arbitrary ISA card with a glasgow? or use a glasgow as a peripheral on an ISA bus?
<cr1901_modern>
whitequark: This is the primary reason I'm waiting for revD :P
<cr1901_modern>
enough I/O to make port-mapped I/O ISA card
<whitequark>
Foone_: both.
<whitequark>
cr1901_modern: no reason to wait for revD
<whitequark>
let me sketch how it'd work
<cr1901_modern>
8 pins for data, you'd need 10 pins min for port-mapped addr space, four for MEMR/W, IOR/W, AEN, and there's prob a few more (but not much) I'm missing.
<whitequark>
cr1901_modern: isa has no bus mastering, right?
<cr1901_modern>
Isn't designed for it, later chipsets do it badly
<cr1901_modern>
I know very little about it other than "it exists as a concept"
<whitequark>
cr1901_modern: can you describe memory and io cycles to me in brief
<cr1901_modern>
AEN is used as a gate to distinguish DMA from a normal xfer. When the BALE _trailing_ edge is detected, the address lines A0-A19 are valid. This is common between memory and I/O cycles
<cr1901_modern>
I/O and memory cycles are distinguished using the SMEMW/R and IOR/W signals respectively
<cr1901_modern>
To add a wait state, pull IOCHRDY low
<cr1901_modern>
And of course the data bits are shared for reads and writes (D0-D7). Writes to the card should be ready once BALE is detected
<cr1901_modern>
You have two clock pins to monitor- CLOCK and OSC. CLOCK is the one you want. OSC historically is the raw input to the 8284 clock generator and chances are is not in phase w/ the system clock.
<whitequark>
wtf
<whitequark>
nevermind go on
<cr1901_modern>
All the other signals I don't think you need to worry about for port-mapped I/O without DMA
<cr1901_modern>
or interrupts*
<whitequark>
is BALE a transaction strobe?
<cr1901_modern>
Huh... I guess it is. Only the trailing edge matters, but I can't say I've looked at oscilloscope traces to see how long it actually lasts
<whitequark>
so how do reads from the card work?
* cr1901_modern
checks
<cr1901_modern>
BALE's trailing edge is synchronous to CLOCK. Once that is detected, IOR/W and MEMR/W will become valid soon after (negative edge?), and you either drive the data to be read onto the bus at that point or you insert a wait state
<whitequark>
any waveform diagrams? or at least peripheral schematics?
<whitequark>
what kind of stupid ass waveform is that
<whitequark>
why does it trigger on both edges
<whitequark>
oh
<whitequark>
oh i see how it works
<cr1901_modern>
On the 8288 ALE also goes high on the negedge
andlabs has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<cr1901_modern>
(Explaining this for the rest of the room for those who don't know) ALE is used by the bus controller to split up the address and the data payload because those pins are multiplexed on the 8088. In terms of ISA however, it's a good synchronization point where you know for sure the address is valid
<whitequark>
cr1901_modern: so here's my suggestion
<whitequark>
make an ISA card with some 5V-tolerant CPLD and a PLL.
<whitequark>
multiply the ISA clock by 6
<whitequark>
(or by 3 and use DDR, therefore removing the pre-divider...)
<whitequark>
then, use 6 pins on the glasgow
<cr1901_modern>
So a CPLD that's a gearbox essentially
<whitequark>
call them... for example, GCLK, GFRAME#, and GAD[3:0]
<whitequark>
for each ISA clock cycle, GFRAME is asserted while the cycle type is driven onto GAD[3:0]
<whitequark>
0000 for idle, 0001 for address followed by 5 nibbles, 01RT for memory/io reads/writes
<whitequark>
a write is followed by 2 nibbles of data. a read is followed by 1 nibble of turnaround, 2 nibbles of data, 1 nibble of turnaround again
<whitequark>
(possibly 2 nibbles of turnaround initially)
<whitequark>
this is well, extensible for DMA, really, if you wanted
<cr1901_modern>
boneless LPC
<whitequark>
thank you.
<whitequark>
i was wondering when someone will get the joke.
<whitequark>
it's like LPC but without all the stupid ass parts
<cr1901_modern>
I would prob forego the 5V tolerant CPLD part and just use level shifter components- 5v tolerant programmable devices (besides greenpak) are dyung
<cr1901_modern>
'dying*
<whitequark>
cr1901_modern: anyway. that thing could be encoded with two nmigen modules, host and device
<whitequark>
depending on whether the host lives in the glasgow or in the CPLD, you can make that either be a master or a peripheral
<whitequark>
Foone_: ^
<whitequark>
like literally just swap them
<whitequark>
it's a SERDES, fundamentally
<cr1901_modern>
Sounds like it'll work just fine. But I'm not feeling well enough to think deeply on it tonight. Thanks for the help :)
<whitequark>
cr1901_modern: if you make that board i can make it work
<whitequark>
awww, hifiic says they do not have OPS/EGS
andlabs has joined ##yamahasynths
ej5 has quit [Read error: Connection reset by peer]
<fseidel>
not quite Yamaha synths, but I recently found this album covering 90s grunge on _really_ cheesy-sounding Moog synths and I think some of you might get a kick out of it: https://www.youtube.com/watch?v=SKgrzTg7Ipc
<fseidel>
okay, not 100% grunge, but definitely 90s
_whitelogger has joined ##yamahasynths
l_oliveira has quit [Quit: ChatZilla 0.9.92-rdmsoft [XULRunner 35.0.1/20150122214805]]
sixtysix has joined ##yamahasynths
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
futarisIRCcloud has joined ##yamahasynths
_whitelogger has joined ##yamahasynths
l_oliveira has joined ##yamahasynths
SceneCAT^APUG has quit [Ping timeout: 246 seconds]