ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
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<cr1901_modern1>
ej5: I'm pretty sure the _earliest_ PCI chipset (forget the part name- datasheet is online tho) didn't support IOAPIC, so you were limited to the AT IRQs only. But good question, should look it up when I have time
<ej5>
had a question about the snake baker, somebody wanted a PCI/PCIe version
<whitequark>
PCIe.
<whitequark>
or do you mean one of those flipping cards
<cr1901_modern1>
futarisIRCcloud: That is sold out sadly
<cr1901_modern1>
But I LOVED the product and I wish I purchased one... ahhh well
* cr1901_modern1
was gifted an actual 5150 board for experiments
<whitequark>
futarisIRCcloud: see the thing is i dont actually like old computers at all
<whitequark>
i just happen to constantly stumble into them
<cr1901_modern1>
clk is 6 times the ISA bus freq for boneless LPC... is that going to be enough (8 data pins + 20 addr pins on the ISA bus)
<cr1901_modern1>
well 10* if you're only using port-mapped I/O
<whitequark>
no, i want memory-mapped
<whitequark>
and it's more than enough
<whitequark>
since on ISA you have SIX cycles to respond
<whitequark>
i mean, it's really overkill
<whitequark>
you need to transmit 8 nibbles
<whitequark>
and then receive 2
<whitequark>
so, you have 12 nibbles (including two bus turnarounds) and 6 ISA cycles
<whitequark>
you could easily multiply it by 4 instead of 6, honestly
<cr1901_modern1>
Oh, the six times comes from addr nibble plus 5 nibble payload
<cr1901_modern1>
which should be the maximum packet len
<whitequark>
yes
<whitequark>
it just makes it slightly more elegant
<cr1901_modern1>
and if you multiplied by 4 instead of six, you'd need more pins on glasgow IIUC
<cr1901_modern1>
20/3 pins
<whitequark>
no
<whitequark>
same amount of pins
<whitequark>
you'd just respond slower
<whitequark>
but since ISA bus cycle times are fixed anyway and there's no way to see if the card responded earlier...
<whitequark>
like, no matter what you do, any ISA bus cycle is 6 ISA clocks
<whitequark>
it's pretty stupid honestly
<cr1901_modern1>
>you'd just respond slower
<cr1901_modern1>
It _does_ work nicer if you do 6 times, because you only have to store the current clock cycle's pins that are ready (e.g. at 4 times, you're still sending out the addr when the next clk cycle rolls around)
<whitequark>
yes
<whitequark>
but it's not super important
<whitequark>
cr1901_modern1: you know what's silly?
<cr1901_modern1>
Lots of things
<whitequark>
i can't find any discrete pll that can multiply 10 MHz by 6
<whitequark>
these are all devices twice older than me...
<whitequark>
well either that or you get like rf shit
<cr1901_modern1>
the phase detector used on the IBM PC's original floppy controller can probably do 4.77 MHz... create your own manual loop filter and then feed it into a manual VCO that's 4.77*6
<cr1901_modern1>
and then divide by six w/ a counter TTL chip
<cr1901_modern1>
Well, that's how the floppy controller does it anyway...
<whitequark>
*tons* of parts that can do PCIe clock
<cr1901_modern1>
yea, not much use for low freq PLLs anymore.
<cr1901_modern1>
hmmm... guessing phase detector chips aren't really a thing anymore either
<cr1901_modern1>
(not that it's difficult to make one on an FPGA)
<whitequark>
you can still get ancient ones
<cr1901_modern1>
right
<cr1901_modern1>
whitequark: What I would do personally is phase detector on FPGA, sigma-delta out, rely on a discrete loop filter cutoff being far below fundamental freq, then use a discrete VCO. Feed that signal back into a "count up to 6" counter, which becomes one phase detector input. And your 4.77MHz clock becomes the other phase detector input.
<cr1901_modern1>
Well I would _test_ that anyway and see how good/bad it works in practice
<whitequark>
I guss
<whitequark>
*guess
<Wohali>
phase detection on square waves is trivial
<whitequark>
oh btw
<Wohali>
analogue solutions work well for other waveforms
<whitequark>
can someone here explain me how to make a working digital domain PLL for the FDC?
<whitequark>
i tried to make one but it doesn't really work
<whitequark>
and i'm not sure why
<cr1901_modern1>
I got a working PLL, but I couldn't explain why it worked
<cr1901_modern1>
so I moved onto something else
<cr1901_modern1>
err, a synchronous counter approach instead*
<cr1901_modern1>
Wohali: Right, these are square waves thankfully. The loop filter is what causes me pain b/c finite wordlength effects bullshit.
<Wohali>
simple xor can work
<cr1901_modern1>
And of course a digital NCO is going to have inherent jitter compared to an analog VCO (even if the NCO _does_ correctly track frequency and phase)
<Wohali>
or you can do the D flip flop style if you want the higher accuracy (and know ahead of time the phases won't be too badly out of phase)
<cr1901_modern1>
Not familiar w/ that approach
<Wohali>
neither needs an FPGA
<Wohali>
that's what the old rca/motorola chips did
<cr1901_modern1>
My problem w/ xor gate is that it can't actually distinguish which signal is trailing or lagging... just that they are out of phase. If you use a small FSM, you can track which signal is trailing/lagging up to 180 degrees out of phase (at which point you have bigger problems)
<Wohali>
well, the assumption is you can adjust the phase of either of the signals to compensate
<cr1901_modern1>
Wohali: Yes, the D flip flop style is the approach I was thinking of, my apologies for not making that clear
<Wohali>
if you put a little delay in the phase detector reset path (on the output of that NAND gate, but before it feeds into the reset terminals) you'll have a forced minimum pulse length and you can avoid the dead zone
<cr1901_modern1>
I couldn't remember the name of it
<Wohali>
these are also frequency sensitive unlike the analogue versions, which may be for or against your intended application
<cr1901_modern1>
I don't remember the details about freq sensitivity
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<cr1901_modern>
futarisIRCcloud: The website for that PCB appears to be down and not in internet archive
<cr1901_modern>
furthermore someone would have to write a USB stack for IBM PC (or if they're doing their own custom ISA system, port an existing embedded one)
<ej5>
the photography skills i picked up have served me well ;)
<cr1901_modern>
haha indeed
<cr1901_modern>
as well as your video skills
<ej5>
also i take a train to work. it's diesel but i think it still counts.
<cr1901_modern>
Sure... diesel is cool too. I would happily take PATCO into work if I worked in Philly
<cr1901_modern>
Though I hear BART kinda sucks
<cr1901_modern>
(through no fault of their own- lack of funding etc)
<ej5>
too many crazy people
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<ej5>
yeah it's just caltrain. they run a few japanese cars though which is interesting
<cr1901_modern>
I suppose I shouldn't complain about BART... the Atlantic City Line, which I sometimes take to the shore, shut down September 4, 2018... it is only going back into service May 12
<cr1901_modern>
MONTHS behind schedule
<cr1901_modern>
guess I should be thankful the repairs worked at all