ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
<cr1901_modern>
whitequark: I would have to see your code, and it's been too long since I did this stuff myself to give you an explanation beyond "here is my code that I've seen work, study it"
<cr1901_modern>
With that out of the way, I would really _really_ advise you not to go the PLL on FPGA route... nothing is there but a world of pain.
<whitequark>
cr1901_modern: are you suggesting analog parts?
<cr1901_modern>
whitequark: A "Digital" PLL is only digital in the phase detector part typically. You can create an "All Digital PLL", where you represent the loop filter and VCO digitally. ADPLL is what I tried to do, and I would advise against it unless you are extremely persistent
<cr1901_modern>
the sync circuit on figure 17 is completely digital, but it's not what I would call a Phase Locked Loop
<whitequark>
cr1901_modern: that can only handle MFM at a specific frequency though, no?
<cr1901_modern>
You should be able to adapt it to other frequencies
<whitequark>
i mean, that means it has to know what kind of encoding it's working with to lock to it
<cr1901_modern>
I don't know how to generalize a PLL like you're asking, and even if I did I'm not sure I would
<cr1901_modern>
(Unless someone was paying me :P)
<cr1901_modern>
>i mean, that means it has to know what kind of encoding it's working with to lock to it
<cr1901_modern>
A synchronous counter should be able to handle Run-Length-Limited encodings (1,3), (2,7), (n,k)... the larger "n" is the higher the frequency that the counter needs to be. But the counter doesn't really care about which RLL scheme you're using.