<_whitenotifier-f>
[yosys-symbiflow-plugins] tmichalak opened issue #18: Add support for SDC constraint propagation through clock primitives - https://git.io/Jf5Bt
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<tnt>
kgugala: I just saw a 1.0 release was posted, does that include global clock buffer fix ?
<tpb>
Title: GitHub - antmicro/symbiflow-arch-defs at global_clock_network2 (at github.com)
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<tnt>
kgugala: tx for the update.
<sf-slack>
<kgugala> still, worth getting it - RAM timings have been improved
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<_whitenotifier-f>
[conda-packages] hzeller opened issue #105: Surelog fails to build becuase cmake is confused about Python version - https://git.io/Jf5wp
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<_whitenotifier-f>
[symbiflow-docs] mithro opened issue #288: No symbiflow-arch-defs output in the ReadTheDocs output? - https://git.io/Jf56Y
<_whitenotifier-f>
[symbiflow-docs] mithro opened issue #289: Python API documentation should be included in the Sphinx output - https://git.io/Jf564
<mithro>
kgugala: Do you have access to the quicklogic forums?
<tpb>
Title: build(deps): bump third_party/prjxray-db from `405c3bc` to `20adf09` by dependabot-preview · Pull Request #1513 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro>
kgugala: I just forwarded you the details -- I believe they should become public today anyway?
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<tnt>
slack (VIOLATED) -22.689 ...
<tnt>
So I just need to double the speed ...
<tnt>
cool cool cool ...
<tnt>
Oh the RAM have a 8 ns clock-to-out, you're killing me here.
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<_whitenotifier-f>
[fpga-tool-perf] HackerFoo opened issue #152: Add design: VexRISC-V Linux LiteX SoC with LiteDRAM and LiteEth - https://git.io/Jf5Db
<_whitenotifier-f>
[fpga-tool-perf] HackerFoo opened issue #153: Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth - https://git.io/Jf5DN