04:17 <HackerFoo> acomodi: With fpga-tool-perf, for `python3 fpgaperf.py --toolchain nextpnr-xilinx --project blinky --board arty`, I get this:

04:18 <HackerFoo> Using nextpnr-xilinx 7e46c6a3703d029c9776d57b64e4ba94f7bc8264

09:40 <hexastorm> hey all, i am building a laser scanhead with a ice40 fpga... but have some problems configuring the flash memory

09:40 <hexastorm> my schematic is here https://github.com/hstarmans/firestarter/tree/master/pi_hat

09:40 <tpb> Title: firestarter/pi_hat at master · hstarmans/firestarter · GitHub (at github.com)

09:41 <hexastorm> cdone pin of my ice40 fpga is low ... i am able to switch the fpga between slave and master mode...

09:41 <hexastorm> but i am not able to write to the flash memory...

09:42 <hexastorm> if i cut the power to the fpga (CDONE pin goes to 1 as it is no longer pulled down by the ice40) ... I am able to congfigure the flash memory

09:43 <hexastorm> so ... i have the feeling i am in the situation that the FPGA is working.. but is somehow interfering with me communication with the flash memory and i cannot disable this

09:45 <Lofty> hexastorm: you should ask in ##openfpga I think.

09:46 <hexastorm> okay thanks lofty!

09:59 <daveshah> If you assert (set low) CRESET and keep it low, then the iCE40 should release the flash

10:03 <hexastorm> if i pull the CRESET low... it does have an effect.. the FPGA is no longer polling the clock pin...

10:04 <hexastorm> i can flip all the SPI lines.. but cannot write to memory.. only receive bytes 255 or slave out seems to remain high

10:05 <hexastorm> could i try programming the FPGA without using the flash memory?

10:07 <hexastorm> ls

10:41 <tnt> hexastorm: did you put a pullup on CDONE ?

10:43 <tnt> nm ... I hadn't read the whole backlog.

10:43 <tnt> My guess is you're just not driving the flash correctly ...

11:17 <hexastorm> yep have a pull up at cdone...

11:23 <hexastorm> also considered the fact i am not driving flash correctly.. but made a board without fpga... ( it works) and on the current board it also works if I disable the supply voltage at 1V... but something must be wrong :-)...

12:04 <tnt> "Error 1:"

12:04 <tnt> Well that's just the best error message ever.

12:55 <hexastorm> okay well i fixed it

12:55 <hexastorm> it is the flash ram chip

12:55 <hexastorm> i dont know how this is possible .. but this chip doesnt work well alongside the fpga

12:56 <hexastorm> i solderd the flash memory from the icezero to my board and this fixes the issue..

12:56 <hexastorm> if i only use the flash memory this also works

12:56 <tnt> After configuration the ice40 puts the flash to sleep.

12:57 <tnt> you need a wakeup command.

12:57 <tnt> (and some flash chips don't support the sleep command and so they work even if you don't wake them up because they never went to sleep in the first place)

12:59 <hexastorm> but will it work with the ice40.. i will look for the wakeup command

13:00 <hexastorm> i am using this chip S25FL064LABMFI010 will look for wakeup

13:03 <hexastorm> okay... the vendor which has working memory is known as micron.. the one without working memory is known as cypress.

13:03 <hexastorm> can't seem to find section with wakeup in the cypress manual

13:05 <hexastorm> In DPD mode the device responds only to the Resume from DPD command (RES ABh).

15:18 <sf-slack> <timo.callahan> My PR #1515 https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1515/ failed a test that seems to be a network issue -- is there a way to restart the test (other than pushing an empty commit)? Here's the log: https://source.cloud.google.com/results/invocations/c416c44e-c593-427c-8e58-c17011c05648/log

15:18 <tpb> Title: WIP -- Initial support for Artix 100t parts by tcal-x · Pull Request #1515 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

15:27 <HackerFoo> timo.callahan: Set the `kokoro:force-run` label.

15:27 <HackerFoo> (I've done it for you)

15:36 <sf-slack> <timo.callahan> Thanks, got it!

16:53 <ryancj14> @acomodi I'm getting an error in fpga-tool-perf when I go into the test folder and run test_all.py where it is unable to import the Timed class from utils. Do you get the same error?

16:53 <ryancj14> from utils import Timed

16:53 <ryancj14> ImportError: cannot import name 'Timed' from 'utils' (/home/student/fpga-tool-perf/conf/src/prjxray/utils/__init__.py)

16:53 <ryancj14> File "/home/student/fpga-tool-perf/test/../fpgaperf.py", line 16, in <module>

18:15 <_whitenotifier-f> [symbiflow-examples] mithro opened issue #19: Change to environment.yml - https://git.io/Jf9rU