00:12 <_whitenotifier-f> [fpga-tool-perf] HackerFoo opened issue #155: Re-running a test gives incorrect timing results - https://git.io/Jf550

00:13 <_whitenotifier-f> [fpga-tool-perf] HackerFoo opened issue #156: Vivado and nextpnr don't accept the same XDC constraint files - https://git.io/Jf55u

00:29 <_whitenotifier-f> [conda-env-make] mithro opened issue #2: Add tests - https://git.io/Jf55Q

00:29 <_whitenotifier-f> [conda-env-make] mithro opened issue #3: Add a Makefile.template file. - https://git.io/Jf555

00:42 <_whitenotifier-f> [fpga-tool-perf] HackerFoo opened issue #157: Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (200T) - https://git.io/Jf5dW

02:50 <_whitenotifier-f> [conda-env-make] mithro opened issue #5: Figure out how to test the cygwin + mingw Windows versions - https://git.io/Jf5Nj

03:25 <_whitenotifier-f> [python-symbiflow-v2x] mithro opened issue #65: Port to using conda-env-make - https://git.io/Jf5AF

04:06 <_whitenotifier-f> [conda-env-make] mithro opened issue #6: Solve disk space reporting on Mac OS X - https://git.io/Jf5xr

05:15 <mithro> https://www.quicklogic.com/qorc/ !

05:15 <tpb> Title: QuickLogic Open Reconfigurable Computing (QORC) Open Source tools | QuickLogic Corporation (at www.quicklogic.com)

05:21 <sorear> !

08:29 <_whitenotifier-f> [conda-env-make] mithro opened issue #7: Fix the Windows build - https://git.io/JfdJR

08:59 <_whitenotifier-f> [vtr-verilog-to-routing] acomodi opened issue #517: New Lookahead map status - https://git.io/JfdTu

10:02 <_whitenotifier-f> [fpga-tool-perf] acomodi opened issue #158: Fix Vivado-Yosys tests - https://git.io/JfdLi

10:08 <_whitenotifier-f> [fpga-tool-perf] acomodi opened issue #159: Get fasm2bels to run also for nextpnr bitstreams - https://git.io/JfdLQ

14:58 <_whitenotifier-f> [fpga-tool-perf] HackerFoo opened issue #162: Documentation for each of the designs tested - https://git.io/Jfdla

15:35 <andrewb1999> Does anyone know of an open source DMA axi ip? Or has anyone been able to get DMA working on a zynq device?

15:36 <Lofty> If it's from anybody, it'll be from ZipCPU

15:36 <ZipCPU> o/

15:37 <ZipCPU> https://github.com/ZipCPU/wb2axip/blob/master/rtl/axidma.v

15:37 <tpb> Title: wb2axip/axidma.v at master · ZipCPU/wb2axip · GitHub (at github.com)

15:38 <andrewb1999> ZipCPU: Thanks!

15:38 <ZipCPU> If you like it, feel free to support me on Patreon: https://www.patreon.com/ZipCPU

15:38 <tpb> Title: Dan Gisselquist is creating FPGA tools | Patreon (at www.patreon.com)

16:31 <_whitenotifier-f> [yosys-symbiflow-plugins] JakubJatczak opened issue #19: Add support for building on Windows - https://git.io/Jfd0Y

16:58 <tnt> Trying to rebulding the S3 timing database using ff_1p210v variant instead of ss_0p990v ... curious to see what that'll be like.

17:07 <_whitenotifier-f> [symbiflow-arch-defs] mithro opened issue #1533: Port to using conda-env-make - https://git.io/JfdEX

17:08 <_whitenotifier-f> [sv-tests] mithro opened issue #878: Port to using conda-env-make - https://git.io/JfdEy

17:09 <_whitenotifier-f> [fpga-tool-perf] mithro opened issue #163: Convert to using conda-env-make - https://git.io/JfdEQ

17:44 <_whitenotifier-f> [fpga-tool-perf] acomodi opened issue #164: Fix fasm2bels issues when running with nextpnr - https://git.io/JfdzY

18:15 <tnt> I have no idea how realistic it is to expect those timings to reflect reality, but it would make for a much nicer device :p

18:16 <tnt> I went from a -36 ns slack violation to a 8 ns slack met.

18:16 <sf-slack> <kgugala> tnt: the ff timings is the fast corner

18:17 <tnt> Yeah, I figured :p and at 1.210v

18:17 <sf-slack> <kgugala> yep

19:12 <tnt> kgugala: btw, I get a lot of stuff like "Warning 4483: Timing edge from usb_I.tx_pkt_I.shift_data_$_DFFE_PP__Q_D_$lut_Y.t_frag.XSL[0] to usb_I.tx_pkt_I.shift_data_$_DFFE_PP__Q_D_$lut_Y.t_frag.XZ[0] will not be created since usb_I.tx_pkt_I.shift_data_$_DFFE_PP__Q_D_$lut_Y.t_frag.XZ[0] has been identified as a clock generator"

19:13 <tnt> and the "Netlist contains 191 clocks" doesn't inspire confidence either ...

19:24 <gromero> Hi. Does symbiflow support currently the BRAM found in ECP5 FPGAs?

19:24 <daveshah> Yes

19:25 <daveshah> the only thing not supported is inference the true dual port mode

19:25 <gromero> daveshah: would you mind to point me to some doc on how to use it?

19:25 <daveshah> Not sure of anything specific, look for simple BRAM patterns in whatever HDL you are using

19:30 <gromero> daveshah: you mean that it's not necessary any specific kind of construct or attribute (let's say, in Verilog) so a BRAM is synthesized? How do I know the BRAM is inferred correctly for instance?

19:30 <daveshah> no, you can look for DP16KD in the output

19:31 <daveshah> if you want to force BRAM you can use the (* syn_ramstyle="block_ram" *) attribute on the memory

19:31 <daveshah> as in Diamond

19:36 <gromero> daveshah: got it, thanks a lot

19:39 <gromero> daveshah: btw, how do you usually "read" the many synthesis output from yosys & friends, like I would like to see all generated circuit down to the FFs used and their connections. Is is possible? It's quite hard to read the $nets too ...

19:39 <daveshah> Have a look at the show command

19:39 <daveshah> https://www.youtube.com/watch?v=a2sLfoinQds

19:44 <gromero> daveshah: awesome, that's what I was looking for!. thx.

20:45 <andrewb1999> litghost: Do you think it would be feasible to support synth IO tiles with multiple IPINS or OPINS? Specifically for routing multiple clocks into an roi like region

23:39 <_whitenotifier-f> [python-symbiflow-v2x] mithro opened issue #67: muxes/use_mux.sim.v test - https://git.io/JfdXp