09:25 <_whitenotifier-f> [sv-tests] wsnyder opened issue #862: New class tests are not legal IEEE - https://git.io/Jf17H

12:19 <tnt> Can someone confirm that ram8k_2x1_cell_macro is actually 2 bock rams of 8kbits ? So there is only 4 of those macros in the whole fpga area in the S3 ?

12:48 <Lofty> mkurc hangs around here, right? I wanna discuss a little bit about the proposed QuickLogic flow

12:48 <Lofty> kgugala too, I think.

13:07 <tnt> It's definitely a LC design that's a bit un-usual.

13:11 <Lofty> Can you use the hard muxes to mux together LUTs?

13:11 <Lofty> I only briefly scanned the architecture manual

13:16 <tnt> I think so. It says it can implement a 8:1 mux in one LC.

13:22 <tnt> LUT1 is implemented with the independent 1:2 mux in the cell. So that might be why they consider it takes "less area".

13:23 <tnt> LUT2 is implemented using the same part of the LC as LUT3.

13:24 <Lofty> Okay, I can understand that

13:24 <Lofty> That being said, given that the timing numbers are available I think they should take the time to use ABC9

13:28 <tnt> ATM I haven't build anything to the point of getting a timing report so I'm not even sure what kind of performance to expect.

13:28 <Lofty> Have you seen the eddie/sta branch, tnt?

13:29 <Lofty> If Yosys has timing information it can at least provide the logic critical path time

13:34 <tnt> Nope

13:35 <Lofty> This was actually created to investigate the ABC9 performance problems you've been having, tnt

13:36 <tnt> Interesting. But note that lately, I haven't had many issues with abc9 even on ice40.

13:36 <Lofty> Does flow3 make any difference for you?

13:36 <tnt> It doesn't always help, sometimes makes it a bit worse, but that's just randomly depending on the design.

13:36 <tnt> flow3 ?

13:37 <Lofty> "scratchpad -copy abc9.script.flow3 abc9.script" before calling the main synthesis command

16:16 <shapr> wow, daveshah got the power: https://twitter.com/latticesemi/status/1269102290767458305

16:46 <tnt> Lofty: I'll keep that 'flow3' in mind and run some tests when I get the chance.

16:46 <Lofty> Sure

16:47 <tnt> Anyone know where the ql_symbiflow script is supposed to come from ? I'm not really planning on using it, but I'd need it at least as example on how to call yosys properly for QL (I know there is more steps than just synth_quicklogic) and how to call VPR at all.