18:16 <topaz> hi all - I've been playing about with a Zynq XC27010 board, comparing bitstreams in Vivado and from the output of prjxray's bit2fasm - am I right in thinking that prjxray is ignoring the PSS[0-4] tiles that mux the PS stuff to the PL fabric? I can't see any mention of it in the FASM

18:28 <topaz> I can see that the db includes pip lists and connections relating to the PSS tiles but there aren't any segbits dbs so presumably the bitstream mapping isn't known

18:28 <sf-slack1> <kgugala> @topaz - PSS doesn't have any bits (it's always there)

18:29 <sf-slack1> <kgugala> the only bits you have to set is the routing between PSS and FPGA fabric

18:33 <topaz> ah ok, so the wiring between the INT_L IMUX_L* tiles along the left hand edge, and the inputs to the PS7 (say, EMIOENET0GMIITXCLK) are fixed?

18:33 <sf-slack1> <kgugala> yes

18:34 <mithro> microcolonel: I don't know about nextpnr for Zynq but there is support in vpr and the symbiflow-examples - https://symbiflow-examples.readthedocs.io/en/latest/

18:34 <tpb> Title: Welcome to SymbiFlow examples! SymbiFlow examples documentation (at symbiflow-examples.readthedocs.io)

18:56 <topaz> kgugala: thanks, that makes sense (I am realising the extent to which the Zynq is just an FPGA with a couple of ARMs crudely bolted on - Vivado gives the impression that lots of CPU-related things are bitstream-level settings when they're actually registers that need loading on boot...)

18:57 <sf-slack1> <kgugala> actually, none CPU setting is configured from bitstream :)

18:57 <sf-slack1> <kgugala> all is done from software

18:58 <sf-slack1> <kgugala> (in Vivado's flow this is done in FSBL)

18:59 <sf-slack1> <kgugala> SDK generates ps7_init.c (and ps7_init_gpl.c, which can be used with U-Boot) - this file defines functions configuring the SoC

18:59 <sf-slack1> <kgugala> if you look at it, it is just a bunch of register writes

18:59 <sf-slack1> <kgugala> *registers

21:22 <microcolonel> hmm

21:22 <microcolonel> I see it now, thanks for the *, mithro