11:42 <_whitenotifier> [prjxray] acomodi opened issue #1540: Investigate PCIE_2_1 PIPs - https://git.io/JtflW

11:46 <_whitenotifier> [prjxray] acomodi opened issue #1541: Investigate PCIE_2_1 configuration parameters - https://git.io/Jtflu

11:48 <_whitenotifier> [prjxray] acomodi opened issue #1542: Add PCIE_2_1 primitive to the tilegrid fuzzer - https://git.io/Jtfl2

19:02 <umarcor> mpictor: see https://github.com/im-tomu/fomu-workshop (examples 'vhdl' and 'mixed-hdl'). Those use Yosys + ghdl-yosys-plugin. Similar makefiles are used in ghdl-yosys-plugin's repo, in microwatt or in https://github.com/dbhi/vboard/tree/main/vga.

19:04 <umarcor> mpictor: find packagin alternatives at https://github.com/hdl/packages (fomu-toolchain is based on fpga-toolchain). VHDL support is tested on: containers, MINGW-packages and fpga-toolchain. It is not tested/supported on other packaging projects yet. Some system packagers such as Arch Linux do have user packages, tho.

19:05 <umarcor> GHDL is available on Debian, Ubuntu, CentOS, Fedora, etc. but I'm not sure about ghdl-yosys-plugin or patched Yosys being available there.

19:08 <umarcor> mpictor: if you are interested in formal verification using PSL through GHDL + Yosys + Symbiyosys + [Z3 | Boolector | Yices2 | Super Prove | CVC4 ], let me know.

19:10 <umarcor> mpictor: WRT OCI containers (dockerfiles) see hdl/containers, precisely the context of the docs: https://hdl.github.io/containers/#_context

19:10 <tpb> Title: HDL containers (at hdl.github.io)

19:13 <umarcor> Examples about using those containers for simulation and/or synthesis of VHDL projects are found in e.g. https://github.com/antonblanchard/microwatt or https://github.com/marph91/icestick-remote. The makefiles are similar to the ones used in ghdl-yosys-plugin.

19:15 <umarcor> having a "higher abstraction level" manager for using containers (instead of Makefiles) is work in progress. PyFPGA has some preliminary support: https://gitlab.com/rodrigomelo9/pyfpga.

19:24 <umarcor> mpictor: after providing all those refs, desired future work is improving the collaboration and coordination with existing SymbiFlow repos. so, adding Verilog to Routing and other missing tools to hdl/containers. E.g. iverilog and verilator should be very easy.

19:25 <umarcor> or, letting SymbiFlows "design management" tools talk to containers.

19:27 <umarcor> there is a parallel working path for building containers and the CI infrastructure that lets SymbiFlow to be self-tested. that is, linting, style, testing, docs, automatic bumping, etc. All of this is already done and working (see antmicro's org too), but using the virtual environments available on CI services (typically Ubuntu).