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<lambda>
is it possible that the examples (xc7/counter_test for arty_35 in my case) require symbiflow's yosys fork? I'm hitting an assert in ABC9 with latest master upstream yosys
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<nickoe>
litghost: How do I run simulation on the counter_test?
<sf-slack>
<kgugala> nickoe: counter_zynq instantiates ps7 primitive and uses Zynq's hard CPU gpios to control the counter logic (enabling counter and changing count direction)
<sf-slack>
<kgugala> apparently github cannot create links from relative gitmodules
<nickoe>
oh, but that is also a bit funky do to it like that?
<sf-slack>
<kgugala> with relative submodules it's easier to handle this in forks
<sf-slack>
<kgugala> this repo is for documentation and it combines info from submodules, so if you work on it you often have to change a few repos at once
<nickoe>
mm, I see
<sf-slack>
<kgugala> with relative submodules you don't need to change the addresses
<nickoe>
Do you happen to know how I can run simulation on the symbiflow-examples?
<sf-slack>
<kgugala> this is a standard verilog code
<sf-slack>
<kgugala> you can use any verilog simulator to simulate this
<sf-slack>
<kgugala> e.g icarus or Verilator
<nickoe>
mm, but how do I do that? I am not really familiar with icarus or verilator. I may have expected it to be a make option.
<sf-slack>
<kgugala> symbiflow-examples repo is to show how to use the FPGA toolchain to build designs and upload them into the FPGA chips
<sf-slack>
<kgugala> make left and right side equal width
<nickoe>
is genfasm single threaded?
<nickoe>
always, or is this just because I essentially only have on source file?
<sf-slack>
<kgugala> i think it is single threaded
<nickoe>
I see, the reg is larger to have a bigger counter reg, but I guess I just need to assigne the appropiate portion of the reg to the leds
<nickoe>
so I think it built it, but I gues I don't have a binary to run the simluation
* nickoe
goes reading that zipcpu post a bit further
<sf-slack>
<kgugala> once you verilate the design you get a C++ model of (a class) you also need some kind of a tesbench - another C++ piece of code where you instatiate the class with the mode, drive it inputs (optionally read oputputs) and push the simulation forward
<sf-slack>
<kgugala> you have to build it all together (just like any other C++ program) linking against Verilator's runtime and run
<nickoe>
well, right now I have nothing more that what you see in the branch
<nickoe>
I assume there is some boiler plate code I need to get
<nickoe>
I try to do "verilator -Wall --trace --cc counter.v BUFG.v --exe --build sim_main.cpp"
<nickoe>
So I am looking for a Vcounter binary in obj_dir, but none exist and I don't get errors with that command.
<nickoe>
or.. I guess I do, it exited becasue of a warning.
<nickoe>
sigh, all this new syntax when used to read gcc errors, %Warning-DECLFILENAME: counter.v:3:8: Filename 'counter' does not match MODULE name: 'top'
<nickoe>
removing -Wall it do build
<nickoe>
a binary that runs forever seemingly.
<sf-slack>
<kgugala> this is what your code do - it runs i until finish is called in verilog
<sf-slack>
<kgugala> I assume your counter does not do that
<sf-slack>
<kgugala> also you may want to dump vcd
<sf-slack>
<kgugala> (so you can watch signal traces later)
<sf-slack>
<kgugala> e.g. with gdkwave
<nickoe>
yeah, that is what I want. Do I need to call dump vcd manually in sim_main.cpp?
<nickoe>
kgugala can I access signals inside the module in the testbench?
<nickoe>
with verilator
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<nickoe>
mmm, I think I made it simulate stuff, but for some reason it does not look like the output of the module with the led wires are changing
<nickoe>
but the counter is running fine
<nickoe>
mmm
<nickoe>
I am not sure I understand why I get this error. All I modified was the counter assignment to the led and add timescale for sim https://dpaste.com/EA5XXBHGA