08:05 <sf-slack> <mkurc> @cr1901_modern: When it comes to QuickLogic the architecture is built using verilog description (.sim.v files) and v2x but currently it relies heavily on v2x features that haven't been merged upstream yet. Xilinx architectures rely on the other hand on hand-written XMLs (but there may be a small piece that uses v2x that I don't know of).

08:06 <sf-slack> <mkurc> @cr1901_modern: And this is only for primitives. The main VPR arch. XML file is generated by a set of Python scripts both for QuickLogic ang Xilinx.

13:20 <cr1901_modern> mkurc: Should I use v2x even without the upstream features? Note: I haven't added any submodules related to my work yet to the symbiflow-arch-defs tree/don't plan to yet

13:21 <cr1901_modern> err, even with* the upstream features

13:21 <cr1901_modern> And I already have v2x cloned locally, and I'm fine using that.

16:03 <Lofty> If/when kgugala gets back, can somebody tell him I can't reproduce the design9 crash he told me about?

16:05 <sf-slack> <kgugala> @lofty I'm here (over slack bridge)

16:05 <sf-slack> <kgugala> try bram design

16:06 <Lofty> As in ram_test?

16:06 <sf-slack> <kgugala> (I misslooked this earlier - it was not desgn9, but bram)

16:06 <sf-slack> <kgugala> in quicklogic/pp3/tests/bram

16:07 <Lofty> ...Can you double check you're on git commit 790569561be5cd979008a17817241e56b1db2775?

16:08 <Lofty> (for Yosys)

16:08 <sf-slack> <kgugala> yep

16:09 <sf-slack> <kgugala> I'm on that one

16:09 <sf-slack> <kgugala> I'll send you synth log