<promach3>
mithro: I had already asked in #freenode_#yosys:matrix.org
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<mithro>
promach3: Sorry, the people in #yosys probably know a *lot* more about formal than we do.
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<sf-slack>
<jgoeders> @litghost Still having some issues with fasm2bels + interchange format. This is what I've done so far: • Downloaded/compiled rapidwright • Installed capnproto • Downloaded capnproto-java, compiled, and added capnpc-java to my PATH • After that I can "cd interchange && make" in rapidwright without error. • However, running fasm2bels test-py still hits several errors like this: ```raceback (most recent call
<sf-slack>
last): File "/home/jgoeders/bfasst/third_party/fasm2bels/env/lib/python3.8/site-packages/parameterized/parameterized.py", line 533, in standalone_func return func(*(a + p.args), **p.kwargs) File "/home/jgoeders/bfasst/third_party/fasm2bels/tests/test_fasm2bels.py", line 108, in test_fasm2bels main() File "/home/jgoeders/bfasst/third_party/fasm2bels/fasm2bels/fasm2bels.py", line 493, in main
<sf-slack>
output_interchange(top, args.interchange_capnp_schema_dir, File "/home/jgoeders/bfasst/third_party/fasm2bels/fasm2bels/lib/interchange.py", line 561, in output_interchange interchange = Interchange(capnp_folder) File "/home/jgoeders/bfasst/third_party/fasm2bels/env/lib/python3.8/site-packages/fpga_interchange/interchange_capnp.py", line 797, in __init__ self.logical_netlist_schema = capnp.load( File
<sf-slack>
"capnp/lib/capnp.pyx", line 4030, in capnp.lib.capnp.load File "capnp/lib/capnp.pyx", line 3293, in capnp.lib.capnp.SchemaParser.load capnp.lib.capnp.KjException: home/jgoeders/RapidWright/interchange/LogicalNetlist.capnp:1: failed: Import failed: /capnp/java.capnp``` I'm probably just missing a simple setup step, but I'm not sure what it is. I'd be happy to update the documentation once I get it running.
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<LoneTech>
making minor progress. xilinx bitgen can actually report the bit and frame locations of all LUTs and RAMs (that are in use in any design) using -l
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<Lofty>
kgugala: Been looking through the test results you've sent me and added them to my chart
<litghost>
jgoeders: How did you install capnproto-java? There was a bug in capnproto-java where it didn't install `capnp/java.capnp`, but I thought I had fixed it.
<litghost>
jgoeders: If you create an issue on fasm2bels with your replication instructions, I take a look and see where your setup went astray
<litghost>
jgoeders: But overall, I think you had the right idea
<litghost>
jgoeders: I see the problem actually. You said " added capnpc-java to my PATH". You want to install capnproto-java, not just add capnpc-java to the PATH
<litghost>
jgoeders: If you don't want to run "make install" on capnproto-java, we have conda packages for capnproto-java etc all
<Lofty>
kgugala: So, top-120-13 is one of the ABC9 regressions, and it can be analyzed by `sta`
<sf-slack>
<kgugala> I suppose this will be good test case
<Lofty>
ABC finds a 474 LC, 78.9 ns logic path
<Lofty>
ABC9 finds a 702 LC, 43.1 ns logic path
<Lofty>
The reason that -D does nothing there is because the 16.8 ns logic target is too aggressive for that design
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<Lofty>
And I bet something similar is happening for soc_litex_pwm
<sf-slack>
<kgugala> yep I think all the regressions are similar
<Lofty>
So if you do a run with `scratchpad -set abc9.D 80000` on that design, ABC9 finds a design with a lot fewer LUT4s
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<Lofty>
kgugala: ^
<sf-slack>
<kgugala> I see, can this parameter be somehow auto calculated? What about the two run approach you proposed yestarday?
<sf-slack>
<kgugala> (I'll run this test case)
<Lofty>
kgugala: you know how e.g. Quartus will ask you to specify the target clock frequency, and complain if you don't
<Lofty>
abc9.D *is* that target clock frequency
<sf-slack>
<kgugala> can we suck in sdc file?
<sf-slack>
<kgugala> and use it to set this?
<Lofty>
That would be feasible, yes
<sf-slack>
<kgugala> I believe we have a plugin for xdc parsing
<litghost>
Once the propagation pass is done, all clock wires should have clock period annotations
<Lofty>
litghost: to my knowledge, the Yosys ABC9 pass doesn't do clock partitioning, and abc9.D is a global parameter
<litghost>
Oph
<litghost>
In the long term that might be problematic
<litghost>
I know many real designs have multiple clock domains
<Lofty>
In the long term, depending on a pass which has a maintainer that is currently on parental leave is more problematic :P
<litghost>
I'd say that just means we have a documentation/testing problem, but sure
<Lofty>
It's uh, not that straightforward
<litghost>
Never is :)
<Lofty>
Anyway, if kgugala can provide an SDC file for the benchmarks (which might require talking to QL), then I'd be happy to plumb SDC to ABC9 support
<sf-slack>
<kgugala> those SDCs should be in QL repos
<Lofty>
I also think tuning abc9.W could be beneficial
<Lofty>
abc9.W is roughly intended to represent typical interconnect delay
<Lofty>
Which is of course very tricky to estimate
<sf-slack>
<kgugala> you can grab it for tests (before we add the rest)
<Lofty>
Noted
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<Lofty>
Funny to note: ABC gets a delay of 11.164 ns, while ABC9 gets a delay of 8.449 ns.
<Lofty>
If you take into account potential interconnect delays, I think that means ABC fails timing
<Lofty>
(for counter_16bit)
<sf-slack>
<kgugala> I think we can have the number for interconnects
<sf-slack>
<kgugala> @mkurc can possibly help here
<sf-slack>
<mkurc> Hello. Indeed the data is present.
<sf-slack>
<mkurc> But defining a single number for LUT-to-LUT connection won't be possible as it depends on the final routing. Nevertheless we can take eg. worst case or average delay and use it in Yosys
<Lofty>
mkurc: as I said, it's difficult to come up with a good number for abc9.W
<nickoe>
acomodi, not it looks for FileNotFoundError: [Errno 2] No such file or directory: '/home/nickoe/symbiflow_install/xc7/conda/envs/xc7/share/symbiflow/prjxray-db/xc7a35t'
<nickoe>
I added "-d {{platform.device}}"
<sf-slack>
<acomodi> @nickoe No, that should be provided for the symbiflow_write_bitstream command only
<nickoe>
acomodi, I am not sure how to actually get the device string properly
<nickoe>
What do you mean?
<nickoe>
ah, right.
<sf-slack>
<acomodi> artix based devices (e.g. xc7a50tfgg484-1) has device name ase `artix7`
<nickoe>
But still, I am not sure if we can get the artix7 string from the current nmigen stuff, but I wonder why it is required. Can't the write_bitstream just fint it?
<_whitenotifier>
[symbiflow-arch-defs] acomodi opened issue #1985: Provide better usage output for the toolchain wrappers - https://git.io/Jtl8l
<nickoe>
but it looks like it tries to find that device folder by itself..
<nickoe>
it moved the DBROOT=`realpath ${XRAY_DATABASE_DIR}/${DEVICE}` up
<nickoe>
mmm, acomodi, but there is still no tilegrid.json
<nickoe>
where is that located?
<sf-slack>
<rsiddiqui> Hey everyone, I hope you all are fine and healthy. I'm Raheel an undergraduate student. I've been contributing to opensource for an year I've developed RISCV single cycle and 5 stage processor using chisel language and with that I have contributed in BURQ IDE for RISCV core testing with that I'm a python developer ranked 42 over all the world in Google Hashcode 2020 extended round. This yearI I'm really passionate
<sf-slack>
about participating in Google Summer of code and couldn't found better organization than symbiflow for it. Can you guys help me If some one new want to contribute he can start? I would love to contribute as I just checked there are really cool projects. symbiflow
<nickoe>
using openocd -f ${INSTALL_DIR}/${FPGA_FAM}/conda/envs/${FPGA_FAM}/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 build/top.bit; exit" does flash and it blinks
<sf-slack>
<acomodi> Great!
<litghost>
Yay!
<nickoe>
I am stuck at fixing the nmigen flashing though
<nickoe>
acomodi, what is that kokoro thing?
<nickoe>
the ci thin is not overly happy, but that does not seem to be caused by my change
<nickoe>
ERROR: Could not find a version that satisfies the requirement rapidyaml (from python-fpga-interchange)
<nickoe>
ERROR: No matching distribution found for rapidyaml
<nickoe>
litghost: why is that rapidyaml not on pypi yet?
<litghost>
We don't have anything on PyPi right now
<litghost>
Wider issue
<nickoe>
ok
<nickoe>
litghost: How long time does those other tests take?
<_whitenotifier>
[python-fpga-interchange] litghost opened issue #11: Remove rapidyaml git+https in requirements once rapidyaml is in PyPi - https://git.io/JtlaV