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<cr1901_modern> mithro: I notice the ice40 backend has a FASM to Icestorm ASCII tool: https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/ice40/utils/fasm_icebox
<cr1901_modern> Is this acceptable for machxo2 (FASM to Trellis ASCII) as well so that ecppack can indirectly work w/ FASM files?
<cr1901_modern> I talked to daveshah in the past about integrating FASM support into ecppack, but I realize now that the names will diverge, and might be easier to write a python script
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<mithro> cr1901_modern: Well, the more things that natively support FASM the better IMHO...
<hansfbaier> mithro: Sorry for not contributing yet to prjxray, it is still a bit ahead of my learning curve, so I made a couple of contributions to the litex ecosystem, because that helps me to advance my project.
<cr1901_modern> mithro: Alright, I'll see what I can do. How bad could it be (famous last words)?
<mithro> cr1901_modern: Getting something done is more important than getting it done right :-)
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<hansfbaier> mithro: I think the best way to learn FPGAs is to work on a concrete project (as you did with the video capture stuff) in mind.
<hansfbaier> mithro: s/stuff/board
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<mithro> hansfbaier: Lots of people find having a project is a good motivator
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<promach3> Anyone familiar with formally verification of `always @(*)` ?
<promach3> as in doing `assert()` for `always @(*)`
<promach3> along side with `for` loop
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<_whitenotifier> [symbiflow-examples] donn opened issue #122: Nothing for Icestorm? - https://git.io/JtCgH
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<LoneTech> one more minor step. I have gen_part_base_yaml modified to read Spartan6 bit files; but it says there's no IDCODE check in my bit file.
<LoneTech> found the idcode in the bit file, now to see why it wasn't identified
<LoneTech> ... and it expects IDCODE to be 1 word, when it's 2. fixable!
<LoneTech> trickier subject: bitgen doesn't support perframecrc or DebugBitstream. I'm getting autoincrement bitstreams
<LoneTech> on the other hand, my bit files are nearly the whole size indicated in UG380 table 5-5, so they might just be fuzzable without addressing? I suspect switching compressed stream on will include the frame addresses. sizes and counts are also listed in UG380.
<LoneTech> but not how many frames per column and such
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<LoneTech> hmm, maybe the missing FAR isn't quite so missing? There does exist a FAR_MAJ write.
<LoneTech> yep, size mismatch again; the FAR_MAJ write is 2 words
<LoneTech> and that writes FAR_MAJ then FAR_MIN, for a full FAR, according to the manual. and prjxray expected only 1 word.
<LoneTech> why does gen_part_base_yaml expect FDRI before FAR?
<LoneTech> kind of feels like I'd have to use compressed bitstreams and fuzzed locations to snoop out actual used addresses
<LoneTech> hm. that enables multi frame write. not sure it ever uses multiple addressing
<mithro> promach3: That is probably a better question for #yosys channel
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<nickoe> mm, litghost do you know of a more coherent way to run nmigen with the symbiflow toolchain, it looks like a bit of streamlining is needed, including the symbiflow_ prefix thing
<nickoe> litghost: nmigen generates this script when enabling the sybiflowtoolchain (I added the prefix in nmigen), but it checkes for some apparently undocumented environment varable which is empty, but is something that it wants to source. Do you know what file that is?
<tpb> Title: dpaste: GD72JMYSC (at dpaste.com)
<litghost> I do not
<litghost> Sorry
<litghost> I work mostly on the p&r side, less on the ecosystem infrastructure side
<litghost> Again, kgugala or tcal are better people to ask
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<nickoe> mm, for the quick logic stuff they are using the prefixed version of the "tools" https://github.com/nmigen/nmigen/blob/adef3b2e7bb1a0aecededd49081df990ec51ab17/nmigen/vendor/quicklogic.py#L39-L46
<nickoe> ok, now synthing with symbiflow
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<nickoe> mmm, not quite there yet, something fails https://dpaste.com/38EHMBFQG
<tpb> Title: dpaste: 38EHMBFQG (at dpaste.com)
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<nickoe> it looks like ..../prjxray-db/xc7a35tcpg236-1/... should be prjxray-db/artix7/xc7a35tcpg236-1
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<litghost> That's likely a mismatch in prjxry-db and the prjxray python library
<litghost> Are you using conda?
<litghost> This is an easy fix either way
<nickoe> litghost: yes
<nickoe> you see the conda path?
<nickoe> mmm, how do I do that?
<litghost> "conda install prjxray-db=v0.0_243_g057e179=20210119_091808"
<nickoe> litghost: This appears to be the fix needed in nmigen, https://github.com/nickoe/nmigen/commit/119c6fd1789e2d397f285d4956034cc4a95f2006
<litghost> That looks right
<nickoe> litghost: https://dpaste.com/9QBHNSP3J
<tpb> Title: dpaste: 9QBHNSP3J (at dpaste.com)
<nickoe> the environment I am using is the one from https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html
<tpb> Title: Getting SymbiFlow SymbiFlow examples documentation (at symbiflow-examples.readthedocs.io)
<nickoe> I mean the one I get by following those instructions.
<litghost> By freezing the prjxray version to a specific comment
<litghost> commit
<litghost> Your error looks like what happens if you don't do that
<nickoe> it looks like this is what I have in the current env:
<nickoe> litex-hub::prjxray-tools=0.1_2697_g0f939808=20201120_145821
<nickoe> litex-hub::prjxray-db=0.0_0239_gd87c844=20201120_145821
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<nickoe> I am not overly familiar with conda, so I don't really understand the error I get when I try your instll command
<litghost> Try "conda install -c litex-hub prjxray-db=v0.0_243_g057e179=20210119_091808"
<nickoe> grep -r 905a6b5b0407b45b6b7484741c8f701dcfa6b81d
<nickoe> I have that change,
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<litghost> Then it should just work
<nickoe> same sort of error with the channel thing
<tpb> Title: dpaste: 69LTC5DS2 (at dpaste.com)
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<nickoe> oh, wait a sec, I think I missed a char in the last command
<nickoe> that does something
<nickoe> The following packages will be DOWNGRADED:
<nickoe> prjxray-db 0.0_0239_gd87c844-20201120_145821 --> v0.0_243_g057e179-20210119_091808
<litghost> There we go
<litghost> Becuase you have the fixed environment you shouldn't have hit an issue
<litghost> I recommend you file an issue on symbiflow-examples with replication instructions, assuming that things are still broken
<nickoe> gotta fixup nmigen first
<nickoe> it does not appear to fix the issye, though
<litghost> That's good!
<nickoe> I mean, I get the same error... ehh why is that good :S
<litghost> Oh, does not :)
<litghost> Anyways, please file a bug with replication instructions, easier to debug
<litghost> The current symbiflow-examples CI is passing, so something is different
<nickoe> welll, my env works for the symbiflow-examples, but remember this is a nmigen project.
<nickoe> litghost: maybe you can try to run the nmigne project?
<nickoe> source your xc7 compatible symbflow env
<nickoe> git clone https://github.com/nickoe/nmigen -b fixup_symbiflow_toolchain_xilinx_7series && pushd nmigen && pip install -e . && popd
<nickoe> git clone https://github.com/nickoe/nmigen-boards && cd nmigen-boards && pip install -e .
<nickoe> export NMIGEN_ENV_Symbiflow=<to something that also sources your env, or maybe something non zero at least>
<nickoe> edit nmigen-boards/nmigen_boards/arty_a7.py and add `toolchain="Symbiflow"` to the construction of ArtyA7Platform
<nickoe> litghost: ^
<Lofty> kgugala: While I read through these results, what's the cell name for a LUT? I see a bunch of *_FRAG cells here
<Lofty> Sorry, for an LC, not a LUT
<sf-slack> <kgugala> its PB-LOGIC
<sf-slack> <kgugala> this is the whole logic cell
<Lofty> Those numbers don't appear to be in the JSONs you sent me
<sf-slack> <kgugala> my bad :)
<sf-slack> <kgugala> I sent you results from yosys (and referenced the ones from VPR)
<sf-slack> <kgugala> I'll fix this in a moment
<Lofty> Got it, thank you
<Lofty> https://puu.sh/Hb6yB/1126b6b8f2.png <-- I presume you've already charted the data, kgugala, but if not
<litghost> nickoe: My recommendation I stated earlier stands. Please write an issue on symbiflow-examples with replication instructions for your issue
<Lofty> kgugala: So, I've been looking through soc_litex_pwm
<Lofty> I can't run `sta` on it, because qlal4s3b_cell_macro is a black box that I don't know how to describe in Yosys
<Lofty> So I'm probably going to have to wait for timing information from VPR there
<Lofty> Same for counter
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<sf-slack> <kgugala> qlal4s3b_cell_macro is a hard CPU
<sf-slack> <kgugala> (sth like PS7 in Zynq)
<Lofty> So yeah, that's not describable to Yosys
<sf-slack> <kgugala> from FPGA fabric perspective it is just a bunch of pins
<sf-slack> <kgugala> (like IO pins)
<Lofty> `sta` seems to assume that primary inputs/outputs come only from top-level module parameters...
<sf-slack> <kgugala> this could be a problem in such devices
<Lofty> Mmm
<sf-slack> <kgugala> this will also impact Xilinx Zynq
<sf-slack> <kgugala> or Intel's socfpgas
<Lofty> Seems I might have to talk to Eddie about that
<sf-slack> <kgugala> makes sense
<Lofty> Or else hack the testbench to make those signals top-level arguments for my own debugging :P
<sf-slack> <kgugala> this may be faster (at least to figure out what is going on in those designs)
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<Lofty> kgugala: okay, running `sta` on counter-ql shows that ABC9 has found a mapping that is about 25% less delay
<Lofty> So that seems to simply be a case of ABC9 having less timing slack
<Lofty> I'm not particularly concerned there, I think; maybe it'd be a good idea to implement a two-pass mapping system
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<Lofty> kgugala: would you mind running a quick test of counter-ql with `scratchpad -set abc9.D 16825` before `synth_quicklogic -abc9 -mult`?
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<sf-slack> <kgugala> sure
<Lofty> This is very much micro-optimisation, but this is to check that a two-pass approach would result in a better area
<sf-slack> <kgugala> better - 26 LCs (vs 34 earlier)
<sf-slack> <kgugala> vs 29 with ABC
<sf-slack> <kgugala> :)
<Lofty> The predicted area formula is trying its best :P
<Lofty> I'm guessing you don't know what the SpDE area is, do you? :P
<sf-slack> <kgugala> does it make sense to run the whole test suite with this tweak?
<sf-slack> <kgugala> No I don't know it
<sf-slack> <kgugala> (the SpDE area)
<Lofty> <sf-slack> <kgugala> does it make sense to run the whole test suite with this tweak? <-- no, but I think it validates the concept
<Lofty> In the cases where it's feasible >.>
<sf-slack> <kgugala> I just started the run - it's just a computer who has to work on this ;)
<sf-slack> <kgugala> I'll send you the results once I get them
<Lofty> So, here's the kinda stupid idea: run ABC, run STA to get an initial delay estimate, run ABC9 using that delay estimate to get better area for roughly the same delay
<Lofty> Hmm... I do know of another tweak I could make, perhaps, but it's incompatible with the one I described above
<nickoe> /home/nickoe/symbiflow_toolchain_deleteme/xc7/conda/bin/conda env create -f /home/nickoe/symbiflow_toolchain_deleteme/xc7/environment.yml
<nickoe> EnvironmentFileNotFound: '/home/nickoe/symbiflow_toolchain_deleteme/xc7/environment.yml' file not found
<nickoe> litghost: mm, what is the point od that coanda env create thing?
<Lofty> ABC9 has a hack constant called W, to represent wire interconnect delay. It has the result of making ABC9 prefer one big LUT to a lot of small LUTs
<litghost> It's the conda equivalent of a virtual env
<litghost> Isolated conda environment
<nickoe> but why does that command error?
<nickoe> I just too it from https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html and added in a script with set -e
<tpb> Title: Getting SymbiFlow SymbiFlow examples documentation (at symbiflow-examples.readthedocs.io)
<litghost> The file is here: https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/environment.yml , I don't know what is going on with your setup
<nickoe> ok, I see
<nickoe> so it epects to use that file for the definiotn of the env, hende the need to sync the symbiflow-examples repo first in the instructions.
<nickoe> litghost: Why is it that those arch defs need to be downloaded manually (the ones that are wgetted in the end of the instructions)? Why are they not installed via coanda?
<sf-slack> <kgugala> @lofty I sent you results with the scratchpad tweak
<litghost> That's TDB, I believe there is a plan to add a conda package for that too
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<Lofty> kgugala: wow, that's...really quite something.
<Lofty> kgugala: okay, here's a different scratchpad hack for you to try: `scratchpad -set abc9.W 1000`
<Lofty> This is absolutely the hackiest of hacks
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<_whitenotifier> [fpga-tool-perf] mithro opened issue #314: Move to using the inbuilt edalize reporting support for collecting resource information - https://git.io/JtWnp
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<nickoe> litghost: mmm, here you have a recipe for my issue https://dpaste.com/6L6NWFGP4.txt
<litghost> Perfect, thanks
<litghost> Please create an issue with that paste in a block quote
<litghost> on symbiflow-examples
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<_whitenotifier> [symbiflow-examples] nickoe opened issue #123: nmigen tilegrid.json path issue when using symbiflow toolchain - https://git.io/JtWWk
<nickoe> litghost: there you go
<litghost> Perfect, thanks!
<sf-slack> <jgoeders> @litghost I'm trying to run fasm2bels (been a while) and running test-py I'm getting failures due to OS.environ KeyErrors on INTERCHANGE_SCHEMA_PATH https://github.com/SymbiFlow/symbiflow-xc-fasm2bels/blob/0cee3d9cf9cb3115b4273b2a65c1ef0bd65692f6/tests/test_fasm2bels.py#L101. Is this a bug, or is there some documentation somewhere I should be looking at that says how to set up my environment with these changes.
<sf-slack> Thanks.
<litghost> See INTERCHANGE_SCHEMA_PATH to point to https://github.com/Xilinx/RapidWright/tree/interchange/interchange