<litghost>
topaz: So the descriptions are consistent. tile_type_*.json lists src/dst for the "forward" enable of the pip, and the "backward" enable of the pip reverses the src/dst
<litghost>
topaz: In theory the timing model supports asymetric timing characterics for the forward and backward enable, but I haven't seen that so far
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<topaz>
litghost: thanks - the confusing thing is that in the vivado-generated bitstream i've been playing with, FASM only outputs one pip for the bidirectional wire (INT_R_X27Y46.LV0.LV18), and it's the wrong way round for the required signal propagation. Only when I add the corresponding reverse pip manually does my silly homebrew net-following script successfully find a path from the IOBUF back to the PS7 (which is what i'm trying to RE)
<litghost>
Can you post the FASM and the Vivado DCP?
<litghost>
We already have a tool (xc-fasm2bels) that can trace nets from FASM files
<litghost>
If your FASM can create the same bitstream that the DCP does, it likely points to something your script is misinterpreting
<topaz>
yeah, more than likely that my script is wrong ;) i'll try that tool
<topaz>
does xc-fasm2bels preserve the wiring? looking at the verilog i can see `.EMIOENET0GMIIRXCLK(RIOB33_X31Y27_IOB_X0Y28_I),`, suggesting that it has correctly identified the connection - i guess the question is whether it observes the direction of the signal when deriving the net or whether it would consider either pip as sufficient for a bidi pip to be a connection (i'll have to look through the code to see)
<topaz>
infact, i can test that easily by manually reversing the problematic pip and seeing if it still finds the connection
<topaz>
and if I do that I get `AssertionError: (153781, 'INT_R_X27Y64', 'LV18', 3193070)` which does suggest that the error is mine, I shall try and figure out what i've done wrong... thanks for the help
<litghost>
topaz: It should preserve the wiring. Its primary purpose in our flow is to convert open tooling output into something that Vivado can consume
<litghost>
topaz: If you find it doesn't
<litghost>
topaz: If you find it doesn't preserve the wiring, please file a bug
<litghost>
topaz: If you look at the TCL you can see the wiring, grep for FIXED_ROUTE
<topaz>
by tcl i presume you mean the xdc file (which does indeed look like tcl) - and yes, it seems to be crossing LV0, i presume the link to LV18 is implicit
<topaz>
(i barely know how vivado works, i only installed it on saturday)
<litghost>
Oh ya, we converted the TCL to xdc (which is TCL like)
<litghost>
Ya, FIXED_ROUTE specified the node at the output of each pip
<litghost>
The source node is implicit
<topaz>
ah yes, and vivado shows LV0 as the output which agrees with that, indeed the pip in the fasm suggests that too (INT_R_X27Y46.LV0.LV18) so I seem to have just got confused!
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