<rqou>
azonenberg_work: there's an interesting dissertation talk that's going to be happening next week
<rqou>
"[eecs-announce] Dissertation Talk: Reverse Engineering of Gate-Level Circuits"
<rqou>
azonenberg_work: i assume you would like me to attend this?
<awygle>
pie__: Bike: you have a launch window every day except for one week every month, during which you can launch almost but not quite all the time
<awygle>
Modulo the usual "where did you come from where did you go" stuff
<pie__>
rqou, ping me when the article is published :P
<pie__>
*dissertation
<pie__>
or if you can get a copy or something :P
<pie__>
qu1j0t3, lol
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<pie__>
im playing silicon zeroes and i cant get the delay for a signal right
* pie__
flails helplessly
<pie__>
i have to delay a signal 3 ticks so i have time to define the initial values for a function, but i get the output of the function one tick late
<pie__>
if i decrease the delay to 2 ticks the inputs are no longer properly initalized
* pie__
ponders maybe the problem is that the overall thing as a feedback loop has 1 delay on writing
<pie__>
its supposed to output 1,1,1,2 but it does 1.1.1.0.2
<pie__>
mumble mumble data flow
<pie__>
(this is totally relevant to fpga :P)
<pie__>
ok i think the issue is the value only actually becomes defined one tick after i need it...but i cant just positive delay the other stuff to make a negative delay because that will just keep the tick offset at a bad value....i have to delay the write address by 1 after init?
<pie__>
but i dont have anything like a line select...*Scratches head*
<pie__>
no that doesnt work. i dont even have any proper comparison operators yet. argh xD
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<pie__>
holy shit.... i implemented >=2 by doing this: (counter-2)-(counter delay 2)==0
<azonenberg_work>
I may have to get some of these at the new place
<azonenberg_work>
i'm always skeptical of these things in public places, you never know if they've been tampered with, but if i buy them from a trusted source its different
<azonenberg_work>
And this one seems to have been pretty exhaustively tested and actually is built to proper standards
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<awygle>
that does seem pretty great. if i owned this place i would put those in.
<awygle>
a little over a year ago i got sick of never being able to charge my phone and bought a 6-pack of two-outlet AC->USB adapters and put one in almost every outlet in my apartment
<azonenberg_work>
yeah i think i'll make almost every outlet have these lol
<azonenberg_work>
at least in the lab and bedroom/office spaces
<azonenberg_work>
no more hunting for chargers etc
<azonenberg_work>
in particular, i have a headlamp
<azonenberg_work>
bicycle head/tail light
<azonenberg_work>
phone
<azonenberg_work>
power bank
<azonenberg_work>
and probably a few other things
<azonenberg_work>
that all need high current charging
<azonenberg_work>
I dont have enough chargers :p
<azonenberg_work>
this way i can plug the bike light in the garage, etc
<awygle>
azonenberg_work: although i suppose it'd be better if it was all Poe :P
<azonenberg_work>
Yes
<azonenberg_work>
PoE would be better, b/c 48V is more efficient over long cables etc
<azonenberg_work>
And can supply enough power to e.g. charge a laptop
<azonenberg_work>
if i ever build a laptop i am seriously considering having it PoE charged :p
<awygle>
by the time you get around to that everything in the world will be "pcie charged" over thunderbolt or whatever
<awygle>
(i don't really keep up with this stuff)
<azonenberg_work>
Well i will still be ethernet for everything
<azonenberg_work>
And ethernet will still be around
<azonenberg_work>
It sticks around as other standards come and go
<azonenberg_work>
Ethernet over twisted pair is older than me
<azonenberg_work>
the predecessor to 10baseT came out in 1988
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<awygle>
huh, i thought you were olderer than me than that
<azonenberg_work>
Nope, i turned 27 this summer
<azonenberg_work>
So i'm about as old as 10baseT and younger than StarLAN
<awygle>
so you only have like 6 months on me then
<awygle>
(well, six months, a PhD, a house, and a wife :P)
<azonenberg_work>
Lol
<azonenberg_work>
Hey, i may have no life
<azonenberg_work>
But what little life i do have is pretty together :p
* awygle
keeps petting his cat while waiting for his frozen pizza to finish cooking
<azonenberg_work>
If it makes you feel any better i am sitting alone in a hotel 2500 miles from the house and wife
<azonenberg_work>
eating day-old pizza hut pizza from the microwave
<awygle>
lol
<azonenberg_work>
Because, even when work is footing my travel bill
<azonenberg_work>
i eat like a grad student :p
<azonenberg_work>
Buy a pizza for dinner, eat a few slices
<awygle>
i feel great, actually. i'm pretty happy with my life
<awygle>
also the second cat just came over so i'm twice as warm now
<azonenberg_work>
Lol
<awygle>
(does make it hard to write code tho...)
<azonenberg_work>
$WIFE can't wait to get a pupper
<azonenberg_work>
But we want to get the house somewhat fixed up first
<awygle>
a pupper is fine too
<awygle>
i've always been a cat person tho
<azonenberg_work>
She's had dogs her whole life
<azonenberg_work>
Even the aunt she was staying with (just happened to live near where she went to school) had a little furball
<azonenberg_work>
then she moved in with me in a rental with a no-pets policy
<azonenberg_work>
So she's been going through pupper withdrawal ever since we got together lol
<azonenberg_work>
and is super excited about finally being able to have one
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<rqou>
doggos are much fun
<rqou>
a friend is currently dogsitting three in addition to their two regular ones
<rqou>
walking them is a whole-family endeavor
<azonenberg_work>
Lol
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<rqou>
one of my friend's doggos actually seems to know that i always pet him
<rqou>
but this dog also knows that a third friend is even better at giving pets
<rqou>
so whenever the third friend shows up, the doggo abandons me :P
<fouric>
azonenberg_work: to be fair, pizza is pretty dang tasty
<awygle>
the gym dog at my gym always comes over for pets between sets
<awygle>
she is ancient and adorable
<rqou>
my friend's doggo is apparently quite good at begging
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<rqou>
doing things like refusing to eat dog food and demanding human food
<awygle>
my cats only get human food if i put it in their bowls
<awygle>
i found out today they don't like pepperoni
<rqou>
you and whitequark can work together to study #catcognition
<awygle>
i have been trying to apply some of those principles
<awygle>
but i think most of the time they meow they really do just want pets? they are the clingiest cats i've ever had
<awygle>
also i'm pretty sure the fuzzy one is slightly slow. he was upset this morning because he couldn't get into the bedroom because he couldn't figure out that he had to go down the cat tree first
<awygle>
"i can't walk, there's no ground!"
<awygle>
"...the ground is behind you."
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<pie__>
(turns out i was just supposed to put 3 latch registers in a row and tap them...)
<pie__>
oh NOW they give me function blocks, the bastards :P
<awygle>
ohhh man i haven't thought about this show in a decade
<cr1901_modern>
I mean the finale aired 8 years ago lol. I just still enjoy it b/c apparently that part of me never grew up
<rqou>
it's apparently good for triggering bugs in dolphin :P
<awygle>
i used to love this show. although probably a nontrivial amount of it was because it annoyed my parents
<pie__>
rqou, yeah its called silicon zeroes
<cr1901_modern>
ed edd n eddy breaks dolphin?
<rqou>
is it a nerdsnipe game like shenzhen io?
<pie__>
yeah but i kinda didnt like shenzhen because the extremeley limited microcontrollers were annoying
<pie__>
we'll see about this lol
<pie__>
i guess i like these games until stuff hits the fan? xD
<rqou>
hmm, i'd actually like to see SexyCyborg do a let's play of shenzhen io :P :P
<pie__>
then again i wastes like....3 hours on that one level 0_0
<pie__>
then i need to switch to studying for my logic and set theory clas ;_; which i like, just yesterdays test screwed up my study time for todays test...
<rqou>
O_o logic and set theory is part of your CS curriculum?
<awygle>
i installed Doki Doki Literature Club but it's probably too late to start it tonight
<rqou>
weeb :P
<pie__>
rqou, nope, i dont have a cs curriculum
<pie__>
im doing physics remember :P
<awygle>
rqou: no u
<pie__>
no its not part of the pysics curriculum either xD
<rqou>
i don't remember
<pie__>
i have unhealthy mathematical leanings :P
<rqou>
lol me too
<pie__>
but this will come in useful for my unhealthy program analysis leanings
<awygle>
rqou: you do rust, have you used nom?
<rqou>
no
<cr1901_modern>
nom is annoying to use, but it works
<awygle>
s'breakin' my brains
<cr1901_modern>
anything macro heavy is annoying to use
<awygle>
can't figure it out
<cr1901_modern>
awygle: Regarding DDLC: Just Monika.
<cr1901_modern>
It'll make sense soon
<awygle>
cr1901_modern: lol noted
<awygle>
i haven't played a VN since college probably but i know they tend to hook the same part of my brain that book-books do, meaning that if i start playing tonight i will also finish tonight lol
<cr1901_modern>
Best one to play is YU-NO IMHO
<rqou>
ah, so you actually play it for the plot, not the "plot"
<awygle>
cr1901_modern: i know, i follow you on twitter :P
<cr1901_modern>
Then why haven't you played it yet :)?
<awygle>
because it's not on steam
<awygle>
and therefore requires >0 effort to get and install :P
<cr1901_modern>
And it never will be.
<cr1901_modern>
Ask pie__ how they did it
<awygle>
i'll add it to my list of media to consume
<awygle>
once i finish ancient magus' bride and ddlc maybe
<awygle>
barely have time to weeb these days
<cr1901_modern>
YU-NO just is one of the few stories for me that has an excellent build up as well as payoff. I really can't describe it. It has to be experienced.
<rqou>
i just look at what memes Fiora posts :P
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<cr1901_modern>
Yea I downloaded I/O (which she loves) but haven't started it yet
<awygle>
cr1901_modern: here's my test - do you wish you could forget it so you could experience it for the first time again?
<cr1901_modern>
yes
<awygle>
mk
<pie__>
cr1901_modern, the save system in yuno intimidates me
<pie__>
(still)
<pie__>
(i havent played it since)
<cr1901_modern>
:(
<cr1901_modern>
I would suggest reading the spoiler-free guide then
<cr1901_modern>
(on VNDB)
<cr1901_modern>
the Saturn port recognized you needed to start w/ more jewels
<cr1901_modern>
so they give you 4 instead of 2
<pie__>
hmmm MEM HAX
<rqou>
Saturn port?
<cr1901_modern>
Yes, YU-NO had a saturn port
<cr1901_modern>
pie__: and since you find your first jewel almost immediately, in the Saturn port you start w/ 5/10 instead of 3/8 jewels
<rqou>
ooh, it's actually from that era
<rqou>
not some guy doing it for lulz
<cr1901_modern>
Right
<awygle>
is this the kind of thing i'll need to run a Windows 98 VM to play?
<cr1901_modern>
no
<cr1901_modern>
runs fine on Windows 7 64-bit
<rqou>
because the lulz retro targets are usually nintendo systems or dreamcast
<pie__>
awygle, i ran it in wine
<rqou>
since afaik saturn is a _pain_ to program
<awygle>
it's weird that there's this little hole in time where wine is actually the most reliable way to run windows programs
<pie__>
worked fine minus alt-tab breaking fullscreen but thats prob not game fault
<awygle>
like Sonic R is a game i love but essentially cannot play
<rqou>
saturn is a pain to even hack because all the connectors you can plug boards into don't take 63 mil pcbs
<cr1901_modern>
pie__: Where did you get stuck last?
<cr1901_modern>
it's fine what you say is prob not a spoiler
<rqou>
unless the hack doesn't involve the saturn at all and only involves desoldering the cdb chip *cough* *cough*
<awygle>
did anyone play Prop Cycle when they were kids?
<awygle>
i wonder if that's in MAME...
<rqou>
hmm, apparently has a weird gpu chip
<cr1901_modern>
I'm not really interested in arcade games after the early 90's, so no
<cr1901_modern>
about the time where they stop being able to distinguish themselves from consoles or PCs
<awygle>
Prop Cycle had a bigass bicycle attached to it so it was reasonably distinguished imo
<cr1901_modern>
So did the SNES :P
<cr1901_modern>
(well an exercise bike)
<awygle>
just a weird nostalgic brain wrinkle sparked by discussion of the saturn lol
<rqou>
oh yeah, amazingly i haven't gotten any saturn drama on me yet
<cr1901_modern>
Maybe that's b/c nobody knows you have the firmware
<rqou>
the slides are public
<cr1901_modern>
rqou: This isn't a reflection on what's fair in the world, but Dr. Abrasive's video alone got like 2 million views :P
<rqou>
wtf
<rqou>
but then again i've been keeping quiet about it
<cr1901_modern>
prof* abrasive
<fouric>
rqou: wait, you have the sega saturn firmware?!?!
<rqou>
the cdb firmware?
<rqou>
i have one version
<rqou>
different from Abrasive's
<fouric>
cdb?
<fouric>
wait
* fouric
reads more closely
<rqou>
cd block
<fouric>
oh
<rqou>
the bios is trivial to get
<rqou>
the ones that are missing are afaik the system management 4 bit thingamajig and the cd mechanism microcontroller
<pie__>
cr1901_modern, i havent played since we last talked :9
<pie__>
still easier than the previous level that needed like 7 blocks total
<pie__>
damn, par is 18 blocks, im down to 19 ...jesus
<pie__>
there isnt even anything left to remove xD
<pie__>
inb4 throw yosys at this thing
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<rqou>
pie__: i wonder how Clifford would feel about "fantasy" backends for yosys?
<rqou>
e.g. redstone or whatever vidya you're playing
<pie__>
lol
<pie__>
that would be kind of funny
<pie__>
how do you make a multiplexer from demultiplexers
<pie__>
err, other way around
<cr1901_modern>
I've thought about doing a TTL backend to yosys (synthesize to the equivalent 7400 series chips) as a joke, but kevtris talked me out of it.
<cr1901_modern>
Basically too many chips w/ async latches to make it worthwhile
<rqou>
i mean, the standard yosys cell library can be implemented with 7400 logic
<rqou>
there's no "minimize total chips with clever tricks" though
<cr1901_modern>
it's no fun if I do "techmap $alu to $whatever_7400_chip_is_an_alu" :P
<rqou>
you can tell abc to techmap down to only certain gates
<fouric>
i would pay money for yosys to have a redstone backend
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* fouric
was planning on paying money anyway
<fouric>
but i'd actually *buy* that backend
<fouric>
hm, does yosys actually have a frontend/backend split proper
<fouric>
any idea how difficult it would it would be to write my own frontend?
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<pie__>
man wtf i have to use decimal addition and a multiplexer to make a demultiplexer and i have no idea how
<pie__>
this game doesnt even have hints
<pie__>
ok i had to cheat...wow wtf
<pie__>
(looked up the solution
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<jn__>
fouric: depends on the language you're targeting in the frontend
<fouric>
jn__: if i'm very comfortable with the language i'm targeting, how are are the yosys-specific bits?
<jn__>
ask rqou, he's been writing a VHDL frontend
<jn__>
rqou: ^
<azonenberg_work>
fouric: apparently some university wrote one for a class
<azonenberg_work>
but it was combinatorial only
<azonenberg_work>
and not super efficient
<azonenberg_work>
no support for sequential logic or timing etc, although i think their PAR did add repeaters to long nets
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<balrog>
azonenberg_work: the closest thing out there for VHDL is ghdl but that's written in Ada
<balrog>
(forget who was asking about it)
<balrog>
cr1901_modern: how about 3 input nor gates (e.g. apollo guidance computer)? LOL
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<awygle>
Bringing up the packing issue again - we don't want to push it into placement because of the technology dependence. What about going the other direction and just synthesizing to the larger blocks from the get go?
<azonenberg_work>
We care about placement within the CLBs due to tech dependence
<azonenberg_work>
I guess we could pack in yosys vs our tool
<azonenberg_work>
But honestly i would rather pack in our tool, it doesnt seem appropriate to do in synthesis
<azonenberg_work>
I would have a packing phase, possibly not using the parallel algorithm, before we jump into the parallel placer
<awygle>
I think you're probably right, I just want to consider the alternative
<awygle>
We could techmap to the SB_ primitives first and then have a coarser techlib for the CLB
<awygle>
(using icestorm as the example)
<azonenberg_work>
I think yosys is a poor choice for packing
<azonenberg_work>
just the way their model is constructed
<awygle>
Would Yosys do a good job of that mapping? I don't really know Yosys well at that level
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<azonenberg_work>
No
<azonenberg_work>
I think not
<awygle>
Mk
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<rqou>
woot, anyone want to try to repro the ME hack?
<rqou>
requires physical access
<rqou>
apparently a classic stack overflow lol
<pie__>
theres only so many exploit classes
<pie__>
:P
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<azonenberg_work>
eh, new ones are always being found
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<azonenberg_work>
rqou: so physical access -> ME root?
<rqou>
yup
<rqou>
might require some downgrading of me firmware i guess?
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<rqou>
azonenberg_work: idle thought: do you think i can fit a usb stack and an ethernet mac in an ice40?
<azonenberg_work>
cant comment on usb
<azonenberg_work>
ethernet, yes
<azonenberg_work>
maybe even a PHY if it has good io cells :p
<rqou>
lol
<azonenberg_work>
lets see...
<rqou>
sb0 has a usb thing, but idk how well it works
<azonenberg_work>
Sooo you have DDR I/O
<rqou>
i do? :P
<rqou>
(i don't know ice40 that well)
<azonenberg_work>
Differential inputs
<azonenberg_work>
On the RX side you can do LVDS up to 400 MHz
<azonenberg_work>
and LVCMOS33 outputs at 250
<azonenberg_work>
So full pre-emphasis might not be possible on the TX
<azonenberg_work>
but i'm pretty confident you could port TRAGICLASER to ice40 if you were so inclined
<azonenberg_work>
might have to tweak some passive values
<azonenberg_work>
but it's totally doable
<rqou>
what about using a real phy?
<azonenberg_work>
a MAC without half-duplex support (why would you want that?)
<azonenberg_work>
is stupid simple
<azonenberg_work>
its basically a CRC calculator and a tiny little state machine
<azonenberg_work>
And a few muxes if you want dual/tri mode support
<rqou>
(somewhat troll): what about tcp offload on ice40?
<balrog>
azonenberg_work: it's funny, I've dealt with laptop docks which have an Ethernet chip that is unable to do half duplex
<azonenberg_work>
Not with a sane buffer size, but UDP for sure
<azonenberg_work>
balrog: lol
<azonenberg_work>
personally i consider half duplex deprecated
<azonenberg_work>
there is no reason to ever use it
<azonenberg_work>
i have never seen hardware unable to do full duplex
<rqou>
10/half?
<rqou>
yes, even broadcom hated this
<balrog>
at the time the university networking group charged extra for 100/1000 and did not offer 10/full
<balrog>
so everyone did awfully slow 10/half to save money
<rqou>
apparently it requires the phy and the switch to both do something special
<azonenberg_work>
Back in 2008 my school had 100/full capable ports in the dorms but many were rate limited by being forced to 10/half
<azonenberg_work>
Now, they've upgraded
<azonenberg_work>
there is no reason to not support 10/full as your lowest option
<rqou>
see, berkeley actually knows how to run a network (even though it looks very legacy)
<balrog>
they've upgraded since but they held out for a while because of revenue reasons
<azonenberg_work>
10baseT is from 1990
<rqou>
gigabit link rate with proper rate limiting
<azonenberg_work>
rqou: yes
<azonenberg_work>
that sounds sane
<azonenberg_work>
i wish i had an ISP that did that
<rqou>
apparently when i was at broadcom i was told there are still customers asking for 10/half support
<azonenberg_work>
...
<rqou>
the use case is something like "combine 100 legacy 10/half devices into one gigabit port"
<azonenberg_work>
let it die
<azonenberg_work>
pllllease
<rqou>
yeah, everyone hated it
<balrog>
ugh
<rqou>
azonenberg_work: do you have a better solution for people with factories full of ancient scada crap? :P
<azonenberg_work>
rqou: replace the ancient scada crap
<azonenberg_work>
:p
<rqou>
but that crap costs far more than a switch :P
<azonenberg_work>
failing that, make a MITM box that bridges 10/half to 10/full with some buffering
<rqou>
that's called a switch :P
<azonenberg_work>
no i mean 2 ports
<azonenberg_work>
that sits inline
<rqou>
2 port switches exist too :P
<rqou>
azonenberg_work: do you think an ice40 can keep up with gigabit?
<azonenberg_work>
It can run at 125 MHz according to the datasheet but you'd want fairly heavy pipelining
<azonenberg_work>
at >125*
<azonenberg_work>
the IOs should be fast enough to do RGMII with the DDR buffers
<rqou>
hmm, now that i think about it, i don't think ice40 has enough clocking resources
<azonenberg_work>
oh?
<azonenberg_work>
if you cheat
<azonenberg_work>
you can loop back the RX clock as a TX clock
<rqou>
clock domain crossing seems much harder on ice40
<azonenberg_work>
Oh? why so
<azonenberg_work>
i mean i know icestorm has sucky timing analysis
<rqou>
there's no xilinx-style distributed ram
<rqou>
that's dual-ported
<azonenberg_work>
Is the block ram dual ported?
<azonenberg_work>
my ethernet mac only uses block ram cross-clock
<rqou>
i think so?
<rqou>
but block ram tends to be precious for other uses
<azonenberg_work>
I need a big enough buffer to store a whole 1500-byte frame
<azonenberg_work>
in each direction
<rqou>
ah, that's true
<azonenberg_work>
to rate match from the internal clock to the network
<azonenberg_work>
Also xilinx distributed ram is combinatorial read
<azonenberg_work>
and clocked write
<rqou>
yeah
<azonenberg_work>
So you dont need two clock inputs
<azonenberg_work>
you need combinatorial read inputs, and a write port
<azonenberg_work>
you could just do a passive combinatorial arbiter to decide who gets to touch the single port at any time
<rqou>
hmm, i don't know if it's possible to fit an ethernet mac, some usb stuff, and some dsp-like stuff all in an ice40 though
<rqou>
(yes, this is yet another probably-won't-get-finished pet project)
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<awygle>
I used, iirc, 100/half on a project once because I was going through a slip ring and couldn't spare 8 wires (but could 4)
<azonenberg_work>
lol
<azonenberg_work>
you can run 100/full over that
<azonenberg_work>
You dont need 8 wires until gig
<awygle>
Isn't that a base T vs base TX thing? I can't remember
<azonenberg_work>
100/half and 100/full both require two diff pairs (4 wires)
<azonenberg_work>
No
<azonenberg_work>
100baseT does not eixst
<azonenberg_work>
exist*
<azonenberg_work>
100baseT4 i think may have used all 4 pairs (8 wires) but i dont know a ton about it
<awygle>
Maybe we just forced it to 100 then... But I know we did something with ethtool
<azonenberg_work>
100baseTX, the standard protocol everyone knows as 100M Ethernet
<azonenberg_work>
uses one diffpair each way
<azonenberg_work>
and afaik half vs full duplex is purely a MAC level thing
<azonenberg_work>
it doesnt literally have the pair changing directions between packets
<azonenberg_work>
It basically just says you can't send while you're receiving a packet
<azonenberg_work>
so just send idles while data is incoming
<awygle>
Certainly sounds saner
<awygle>
... In some ways
<azonenberg_work>
Half duplex in modern ethernet is pointless
<azonenberg_work>
it uses the same number of wires and is slower
<azonenberg_work>
and doesnt really save much complexity in firmware
<awygle>
In other news, I have a chip here which seems unwilling to accept a simultaneous speed change and termination change about, oh, half the time
<azonenberg_work>
wut
<awygle>
If I go from slow+unterm to slow+term and then to fast+term it seems to always work, going straight to fast+term shows a clearly unterminated line half the time
<azonenberg_work>
...
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<fouric>
azonenberg_work: my google-fu is not strong, and i can't find a yosys university project
<fouric>
any chance you have the link still, or, failing that, an extra keyword or two (class name, project name, uni name) that i could use?
* fouric
found rqou's myhdl project but it isn't quite enough
<cyrozap>
fouric: Try searching for "yosys site:.edu"
<cyrozap>
in your favorite search engine.
<fouric>
searching, but still not finding anything
<fouric>
(in google, because duckduckgo still has trouble with more nuanced topics)
<fouric>
top result is OSU's ftp server, which isn't helpful
<fouric>
around the fifth result, "yosys" starts getting omitted entirely
<cyrozap>
"The authors would also like to thank their advisors, who are not aware this work was happening despite the amount of _real_ research work to be done."
<rqou>
lolol
<cyrozap>
[humor, off topic] In this thread, a HN reader doesn't understand the difference between "modulating a signal on top of the reflected energy of a WiFi signal" and "modifying bits transmitted in a WiFi frame" and thinks a 3D-printed object (plus some copper wire) can do the latter, and claims the former is impossible (despite the paper describing how it's accomplished):
<Bike>
wow, i saw that today in a totally different context. news being kind of centralized still weirds me out
<Bike>
i like the related paper where they powered a microcontroller and display from television signals
<cyrozap>
(the linked comment is just the root--the replies are where the gold is)
<fouric>
cyrozap: what search terms did you use?
<fouric>
nobody mentioned anything about minecraft, so i was just doing "yosys backend university project" etc.
<rqou>
hmm, sounds like some conversations got crossed
<fouric>
lolololol
<fouric>
verbal crosstalk
<cyrozap>
fouric: "yosys site:.edu" what literally what I put into DDG.
<fouric>
(this actually happened to me - there was a conversation about property taxes going on in another buffer, and someone on google hangouts asked me for family photos, and i sent them property photos instead)
<fouric>
er
* cyrozap
is confused as to which conversations got crossed
<fouric>
wait
<fouric>
no
<fouric>
this is a different thing
<fouric>
this is a backend for yosys
<fouric>
i was looking for frontend examples
<fouric>
...although this is super cool and i'll take it
<fouric>
er, yeah
* cyrozap
is still confused
* cyrozap
hurt itself in its confusion
<fouric>
lol ):
<fouric>
ok, so i asked general chat about yosys frontends
<rqou>
earlier i was talking about "fantasy" backends for yosys
<fouric>
specifically, how difficult it would be to create one
<fouric>
yeah, that must have been it
<fouric>
azonenberg_work: were you thinking of a different university project that was frontend related?
<rqou>
i don't believe there are any third-party frontends at this point
<rqou>
unless bitstream parsers count
<azonenberg_work>
No i was talking about a redstone back end
<azonenberg_work>
Not a front end
<fouric>
oh kk
<azonenberg_work>
i.e. i dont know anything that will turn redstone into RTLIL
<fouric>
oh, i see
<fouric>
you meant to reply to rqou and got me instead
<fouric>
well, this is super cool and awesome and i'm happy