01:19 <rqou> whee, time to actually start studying for my final tomorrow

01:26 <cr1901_modern> 5 years since I last took a final...

01:30 <pointfree> https://msoeken.github.io/reciprocal.html <--- synthesizing reversible logic with yosys + revkit

02:02 <pie_> <clever> pie_: https://gist.github.com/cleverca22/010456d1d1895f760bd8244fd62ffd9f

02:02 <pie_> <clever> pie_: this is one of the more crazy things ive done, this boots nixos, under xen, under qemu

05:09 <awygle> damn, the LNA on my downconverter has been EOL'd

05:36 <cyrozap> pointfree: I pushed the macrocell model to my psoc-bitstream-parsing-tools repo. I haven't pushed the PLD model yet because I'm still trying to get it to work.

06:27 <pointfree> cyrozap: cool!

07:21 <cyrozap> The plot thickens: For some reason, when I synthesize just the PLD model Verilog module (without the UDB block), the output says that some of the macrocell "selin" and "selout" pins aren't being used, which is odd because they're supposed to be in a chain that goes all the way through the PLD module.

07:21 <cyrozap> So, either Yosys has a bug, or I don't understand Verilog very well.

07:21 <cyrozap> I'm betting on the latter :P

07:35 <cyrozap> pointfree: I pushed the non-functional PLD code.

11:13 <pie_> its been too long since i last read this https://codegolf.stackexchange.com/questions/11880/build-a-working-game-of-tetris-in-conways-game-of-life/142683

16:51 <learnerd> are there any fpga manufacturers that offer an open source toolchain?

16:52 <jn__> i don't think so. but there are open source toolchains for FPGAs (lattice iCE40, most notably)

16:54 <azonenberg> learnerd: None that are officially vendor supported, no

16:55 <azonenberg> I would love if our toolchain for silego greenpak parts ended up like that eventually

16:55 <azonenberg> The vendor is aware of our project and has been very helpful

16:55 <azonenberg> and has gone as far as tweeting links to my tools from their official company account

16:55 <azonenberg> But doesn't ship our tool or anything like that

16:58 <learnerd> ok, thanks for the info

17:00 <awygle> Has anyone been following the Microsemi RISC-V stuff? This Freedom Unleashed sounds.... Extreme

17:00 <awygle> Err, hi-five unleashed rather

17:02 <jn__> extreme in which way?

17:03 <awygle> It has "five 64-bit RISC-V cores running at 1.5 GHz plus" and a PolarFire FPGA (12.7G transceivers)

17:03 <awygle> DDR4, GigE, etc. Giving it the same name as an arduino-compatible seems very strange

17:04 <awygle> I was expecting a Freedom E300 with an Igloo or something

17:04 <jn__> i think the important part of the branding is "Unleashed", here

17:05 <jn__> "Freedom Unleashed" is the name of sifive's "linux-capable" cores

17:05 <awygle> Yeah I guess that means their Linux capable line. The FPGA is still much bigger than I expected tho

17:06 <azonenberg> Sounds like a Zynq competitor

17:06 <azonenberg> But until their toolchain catches up it's dead to me

17:06 <azonenberg> i'm not even going to bother doing bitstream RE if the vendor tools are so broken that i cant run a blinky on my own computer

17:07 <awygle> It looks more like somewhere between an Artix and a Kintex to me. No hard processor

17:07 <azonenberg> wait the five 64-bit cores are softcore??

17:07 <jn__> azonenberg: no

17:07 <awygle> No they're just external

17:07 <azonenberg> oh

17:07 <azonenberg> This is a SoC + FPGA board

17:08 <jn__> that's SiFive's hard IP

17:08 <azonenberg> Not a single board?

17:08 <azonenberg> not a single chip*

17:08 <awygle> Yes

17:08 <jn__> the fpga is effectively the southbridge on that board

17:08 <jn__> more or less

17:09 <azonenberg> ah ok

17:09 <awygle> Seeing as you can't buy either the SoC or the FPGA yet I'd guess it's a ways out but still much more interesting than I expected

17:09 <azonenberg> Welp, heading out to the airport

17:09 <azonenberg> Be back online from the ferry / airport in a bit

17:10 <awygle> Enjoy your trip

17:12 <awygle> I wonder how much Microsemi makes on software licensing

17:13 <rqou> halp halp final exam cramming time

17:13 <awygle> They seem like they might be good "corporate partners" for this project, if we could offer them a leg up vs. Lattice et al

18:38 <pointfree> cyrozap: Have you seen https://github.com/cliffordwolf/yosys/commit/52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e

21:28 <cyrozap> pointfree: Yeah, I saw it when it was pushed last year.

23:03 <rqou> survived finals

23:12 <awygle> rqou: congrats

23:30 <jn__> pie_: nice codegolf thread!