<fouric>
i heard msft is working on a C++ minecraft
<fouric>
maybe that would be efficient enough to run a 32-bit core
<rqou>
rip mods
<cyrozap>
"C++ minecraft"
<cyrozap>
You mean Minetest? ;)
<awygle>
fouric: the Yosys front-ends in the source are the best resources I'm aware of. I feel that most of the complexity is going to be language related - RTLIL is pretty simple
<azonenberg_work>
And honestly i would be happy with a single 7-series slice in redstone
* awygle
vigorously encourages any and all Yosys front-end development
<rqou>
i was going to add an edif frontend
<rqou>
and then clifford warned me not to :P
<azonenberg_work>
lol why?
<fouric>
^
<azonenberg_work>
competing standards?
<rqou>
edif is a clusterf*ck
<azonenberg_work>
Lol
<rqou>
with tons of vendor extensions that are known as "flavors"
<azonenberg_work>
My general interchange format for tools working w/ yosys is their internal json format
<azonenberg_work>
both for synth -> PAR flows as well as RE -> netlist
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* fouric
was planning on developing his own RTL
<fouric>
er
<fouric>
HDL
<fouric>
sorry
<azonenberg_work>
Oh?
<azonenberg_work>
What would be different about it?
<fouric>
it would be a DSL in common lisp
<fouric>
so very easy to manipulate using external tools
<fouric>
and also macros
<azonenberg_work>
So i guess there's a couple of options here
<fouric>
also because i want to learn things
<azonenberg_work>
the tightly coupled option, write a full parser in C++ and feed directly into yosys's internal data structures
<azonenberg_work>
The super-loosely coupled option, where you compile to verilog
<cyrozap>
Oh, wow, I just realized that I may have been overcomplicating my PSoC 5LP bitstream parser. I don't really have to parse anything, I just need to model the UDB in Verilog, dump the config RAM into a bit array, then let Yosys simplify the Verilog.
<azonenberg_work>
And the moderately coupled option, which i recommend for initial experimentation
<azonenberg_work>
Compile to a yosys JSON netlist
<azonenberg_work>
then import the netlist
<rqou>
cyrozap: welcome to the club :P
<azonenberg_work>
This lets read_json do all the work of creating the data structures for you
<rqou>
i do something very similar
<azonenberg_work>
cyrozap: Have you seen my talk?
<rqou>
i write verilog models for each major block
<cyrozap>
rqou: lol, you did that, too?
<rqou>
and then i emit yosys json instantiating them
<fouric>
hm...HDL->netlist sounds like the tricky part then, i guess
<azonenberg_work>
i think i uploaded pdf slides somewhere but cant recall where
<cyrozap>
azonenberg_work: Oh, cool, I hadn't seen that. Thanks!
<azonenberg_work>
cyrozap: This is basically how our RE flow already works for greenpak and coolrunner etc
<azonenberg_work>
You create a verilog model of every primitive, you create a JSON netlist instantiating each primitive
<azonenberg_work>
then you techmap and flatten
<azonenberg_work>
then optimize
<azonenberg_work>
now you have a technology-independent IR representation of the circuit
<azonenberg_work>
Which you can then start lifting up to increasingly more abstracted representations
<azonenberg_work>
I'm giving a 2-hour talk on this work to christoph paar's research group at RU Bochum next week
<azonenberg_work>
sorry, not the research group - to a class on hw sec the group is teaching
<azonenberg_work>
it's basically the talk i linked you (which is how they found me) glued onto the end of my 2015 REcon talk on coolrunner bitstream RE, plus some of me and rqou's new results in the middle to kinda bridge the gap
<awygle>
I wish everybody would stop compiling to verilog, but I admit that's an irrational bias
<rqou>
there's no better IR
<azonenberg_work>
rqou: yosys json
<awygle>
But there should be
<azonenberg_work>
seriously
<rqou>
yosys json is not a standardized IR
<azonenberg_work>
If clifford actually wrote a spec
<azonenberg_work>
it could become one
<awygle>
Isn't json too loosely specified itself?
<rqou>
there's already two different not-bug-for-bug-compatible implementation of yosys json :P
<awygle>
For Christmas will somebody break the Yosys front and back ends out into a library that can be linked to?
<awygle>
It would make me so happy
<rqou>
already "exists"
<rqou>
libyosys
<rqou>
no idea if it actually works or not though
<awygle>
Wait what is this really?
<rqou>
it's still c++ though
<rqou>
so not ffi-friendly
<awygle>
Tru
<awygle>
And it's too objecty to be amenable to an easy c wrapper I guess
<awygle>
Still cool
<awygle>
Lol there's a feature request to make libyosys more friendly and Clifford's response is "yeah. I'm not going to do that"
<azonenberg_work>
i dont blame him
<azonenberg_work>
lots of work for no real benefit unless you don't like writing tools in C++ :p
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<awygle>
At the risk of getting soap boxy, imo the biggest thing holding back the open source HDL community is that nobody can use anybody else's parsers
<rqou>
the incomplete parser i wrote is intended to be usable in all languages
<rqou>
but in reality it isn't quite
<azonenberg_work>
awygle: i dont think so
<azonenberg_work>
Yosys is pretty much dominating the open HDL field at this point
<azonenberg_work>
What's holding it back is the lack of people writing more plugins for better optimizations and tech libraries
<azonenberg_work>
or do you mean research into new languages?
<rqou>
er, some academics still insist on using odin it seems
<awygle>
azonenberg_work: I mean a lot of things. But there are a minimum of four open source verilog parsers (probably many more) and none of them AFAIK supports SystemVerilog beyond the trivial
<awygle>
What's more I bet even the quantity of verilog they support differs, though I can't prove it
<azonenberg_work>
awygle: My solution to that is to have yosys implement the rest of systemverilog and forget the rest :P
<azonenberg_work>
it's pretty good, and its permissively licensed unlike a lot of the copyleft tools
<azonenberg_work>
So it has the potential to dominate without licensing issues blocking use in other projects
<awygle>
If I had infinite time I'd write an RTLIL version of iverilog and port the ghdl parser to emit RTLIL
<rqou>
i gave up on that second part
<awygle>
But since I can't extract RTLIL from Yosys (without reimplementing it) I can't actually do those things in a useful way
<rqou>
unless you really like ada and a ginormous multi-kLOC recursive descent parser
<awygle>
(shelling out to Yosys is an unacceptable solution on aesthetic grounds even if for no other reason)
<rqou>
yosys can dump ilang, which iirc is a textual representation of rtlil?
<awygle>
rqou: yeah that's the actual solution. Output ilang or json. But then you need an ilang or json parser. Hopefully easier tho
<rqou>
so i'm not sure exactly what you're trying to achieve, but clifford did tell me that the yosys frontend could use a rewrite
<rqou>
since it's the earliest part of the codebase
<awygle>
I'm not actually trying to achieve anything (no time), just this is a hot button issue for me so I got all soap boxy even though I said I wouldn't lol
<azonenberg_work>
parsing yosys json is way easier
<azonenberg_work>
also i'd rather kill iverilog and improve yosys's simulation support
<rqou>
i mentioned that and clifford wasn't a huge fan
<azonenberg_work>
iirc there is a simulator based on all of the infrastructure used for formal
<azonenberg_work>
That said, the majority of my work these days doesnt even involve a lot of sim
<azonenberg_work>
I do formal and FPGA
<awygle>
I am instinctively against agglomerating all resources into one megaproject
<awygle>
But again, that's my bias
<rqou>
anyways, clifford wasn't a fan because all of the sim-only hdl features would make things way way more complicated
<azonenberg_work>
ah i see
<azonenberg_work>
In that case you might need a separate parser anyway
<rqou>
afaik the yosys sim is a netlist/graph-traversal-based sim, not an event-based sim
<azonenberg_work>
Because yosys's parser probably doesnt handle the sim-only stuff at all
<balrog>
it seems like its functions are pretty short
<rqou>
afaik this difference matters once you start triggering race conditions and having weird sensitivity lists
<rqou>
for vhdl, the parser is only part of the problem
<azonenberg_work>
rqou: my response is to say, all level-triggered sensitivity lists are treated as always @(*)
<azonenberg_work>
in fact, my coding policy bans anything else :p
<awygle>
I wonder if RTLIL is fundamentally incompatible with a compliant simulator. In an information theory way I mean.
<balrog>
azonenberg_work: does the spec allow it? :D
<balrog>
awygle: megaprojects are usually split into small projects for a good reason :)
<balrog>
err, small subprojects
<awygle>
balrog: or several reasons, even
<rqou>
what about the company that had a mega project so mega that it ended up including a rewrite of their vcs because the vcs didn't scale enough? :P
<azonenberg_work>
lol
<azonenberg_work>
you talking google?
<rqou>
does any other company fit the description?
<awygle>
MSFT?
<rqou>
oh right
<qu1j0t3>
otoh, google is famous for monorepo
<azonenberg_work>
Yeah i know
<awygle>
Monorepos are another thing I hate aestheticly while intellectually acknowledging that they have some benefits
<rqou>
i like monorepos only because git sucks at subrepos
<balrog>
is git-subtree a part of git now?
<awygle>
imo that is a reason to fix git not abandon subrepos
<azonenberg_work>
awygle: the only reason i no longer monorepo everything (like i did back in my SVN days)
<azonenberg_work>
is that i wanted some of my projects, like jtaghal, to be usable standalone by people working on non-antikernel projects
<azonenberg_work>
Instead i monorepo and fork out subprojects to submodules
<azonenberg_work>
but from my perspective azonenberg/antikernel is still the primary repo for that whole effort
<azonenberg_work>
and the submodules are just there so you can get jtaghal without pulling in all of antikernel
<awygle>
I have a lot of crotchety old man opinions tonight but my scope just crashed because I turned a channel off so I think I get some slack lol
<azonenberg_work>
lol
<azonenberg_work>
i've crashed my lecroy's firmware pretty often
<azonenberg_work>
Have not crashed my R&S PSUs yet
<azonenberg_work>
but that may just be b/c they're newer and i havent used them as much :p
<awygle>
Also this scope thinks 250Msps is 2.0 Gsps
<azonenberg_work>
lolwut
<azonenberg_work>
How does that work?
<awygle>
I open the sample rate box, type 250M, hit OK, and the box says 2.0G
<awygle>
*shrug*
<awygle>
125M and 300M work fine
<azonenberg_work>
lol
<azonenberg_work>
on my lecroy i dont even set sample rate
<azonenberg_work>
I set the capture duration and max depth
<azonenberg_work>
and it calculates the rate
<azonenberg_work>
its kinda awkward at first but you get used to it
<rqou>
i'm waiting for the scope to troll you and set an unusable rate :P
<azonenberg_work>
I generally try and set the depth deep enough that i stay at max sample rate
<azonenberg_work>
unless i am doing a really low speed signal like rs232
<azonenberg_work>
One thing i still have to work on is how to have libscopehal handle this
<azonenberg_work>
as far as how to actually set the capture config
<rqou>
i once tried to capture i2c on a 10 or 20 gsps scope
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<rqou>
that was fun
<azonenberg_work>
right now i require yo uto use the scope gui to set all of the stuff up
<azonenberg_work>
then my app just postprocesses
<rqou>
(the coworkers then found a more appropriate scope)
<azonenberg_work>
i cant even set the trigger level :p
<azonenberg_work>
lol wait did it not support lower rates or something?
<rqou>
only somewhat lower
<azonenberg_work>
When i build my scope, it will run at max rate all the time, and lower rates will simply decimate in the FPGA
<awygle>
This is a 20Gs scope currently capturing a 10M signal
<azonenberg_work>
say, sum 1024 samples and shift right 10 bits
<rqou>
still better than a 400k signal
<awygle>
Tru
<azonenberg_work>
I may or may not have a proper DSP LPF depending on how far you're decimating
<azonenberg_work>
but as much as possible, the intention is to run at max sample rate and stream the full-res capture to the PC
<azonenberg_work>
then figure out the details in post
<azonenberg_work>
When you have 4 GB of capture memory and 10 or 40 Gbps to the PC
<azonenberg_work>
there's no reason to ever do anything else :p
<awygle>
Except your pc probably can't crunch 40Gbps in real time
<azonenberg_work>
awygle: actually, if i GPU accelerated the rendering
<azonenberg_work>
stream sample data into a vertex buffer object then render
<azonenberg_work>
I could probably get close
<awygle>
I'd be really interested to see that
<azonenberg_work>
The short term design will be 10 Gbps max throughput
<azonenberg_work>
When i build the full-scale starshipraider, with the four io cards and 10 Gbps optical LAN port
<azonenberg_work>
I am planning to make a 10 Gsps DSO card for it
<azonenberg_work>
with 1 GHz bandwidth
<azonenberg_work>
TI has a nice ADC for like $300 that is four 1.5 Gsps ADCs interleaved to 5 Gsps
<azonenberg_work>
four 1.25*
<azonenberg_work>
if i phase shift just right i should be able to combine two into a 10 Gsps ADC
<azonenberg_work>
Only about 7 bit resolution iirc, but still thats not a bad price for a 10 Gsps ADC
<awygle>
Doesn't linear or someone have one you can just buy?
<azonenberg_work>
Then i'll have to do the AFE
<azonenberg_work>
awygle: Not that i know of
<azonenberg_work>
fastest single ADC i've seen with >3 bit resolution is that chip
<azonenberg_work>
The runner-up is another TI part that's 4 Gsps but a single folding interpolating converter, not interleaved
<azonenberg_work>
and 12 bit resolution
<azonenberg_work>
That one is $2000 per chip
<azonenberg_work>
Anyway, what i was getting at is
<azonenberg_work>
10 Gsps * 8 bits is 80 Gbps, so i obviously cannot stream realtime to a PC nonstop
<azonenberg_work>
however, what i could do is capture say 1M points then send it out, then another 1M points, etc
<azonenberg_work>
Let's say 1M points so 1 MB / 8 Mb per waveform, at 10 Gbps that's 0.8 ms - round to 1 ms for protocol overhead
<azonenberg_work>
I could get 1000 WFM/s at 1M point capture depth
<azonenberg_work>
saturating 10GbE
<azonenberg_work>
the actual capture would be 1GB/s
<azonenberg_work>
So i'd be actually capturing approximately 10% of the time, limited by the network
<awygle>
That's what this scope looks like at high rates and auto trigger
<azonenberg_work>
Anyway, so what i'd do in that case
<azonenberg_work>
(and probably will do at some point anyway for scalability reasons)
<azonenberg_work>
is make a brand-new OpenGL waveform viewer app
<azonenberg_work>
Stream waveforms to the GPU at 1 GB/s
<azonenberg_work>
then do "digital phosphor" compositing and eye processing on the GPU
<azonenberg_work>
in some combination of shaders and OpenCL/CUDA
<azonenberg_work>
My current cairo renderer is already hitting scaling limits at 10M points on the lecroy when zoomed in far
<azonenberg_work>
tl;dr cairo and GTK fail hard when you have a virtual viewport more than 32768 pixels wide
<azonenberg_work>
So i need to fix it, and as part of the fix i am considering moving to OpenGL rendering rather than just doing my own virtual framebuffer in cairo
<awygle>
I can't remember exactly but iirc you can do DMA from NIC direct to gpu memory now
<rqou>
afaik it needs a quadro
<awygle>
I know you can do it from infiniband or iwarp but I thought I remembered 10gbe support as well...
<azonenberg_work>
I can still go through the PC if i have to
* azonenberg_work
checks ram bandwidth of a current gen xeon
<cr1901_modern>
awygle: So you finally installed it :)?
<awygle>
cr1901_modern: i started DDLC
<cr1901_modern>
Bahahahahahahahahahaha
<awygle>
i feel like my antivirus should have blocked this game
<cr1901_modern>
Just Monika. That's all you need to know :D
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<cyrozap>
lol I just realized something
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<cyrozap>
If I make a Verilog model of the PSoC UDBs and interconnect,
<cyrozap>
we could in theory build our own PSoC ASIC.
<cyrozap>
Of course if we did that we'd 100% be in violation of Cypress's patents, but it's still kind of fun to think about :D
<pointfree>
cyrozap: ...but I'm not really sure how the permutable routing is implemented. Also, there's the analog blocks.
<pointfree>
*there are
<cyrozap>
Well, yeah, it wouldn't be a 100% perfect clone. We'd need an ARM core for that, anyways.
<cyrozap>
And remind me which part is the "permutable routing"?
<pointfree>
cyrozap: it's not a part, it's the flexibility of the routing fabric.
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<cyrozap>
pointfree: Oh, but don't we have the information from the patents and the bit mapping you've done? Is that not enough?
<cyrozap>
anyone: Just to confirm, `(bits[0] | bits[1]) == (bits != 0)`, right?
<awygle>
cyrozap: if bits is [1:0], yes. although the != 0 comparison is a bit iffy since 0 will be 32 bits
<cyrozap>
awygle: Ok, that's all I needed to know. In the real code I'm effectively doing that over an 8-bit vector, and I didn't want to have to write out every OR operation for every bit. The result is assigned to a 1-bit wire, so the 32-bit thing shouldn't be an issue.
<cyrozap>
Thanks again!
<awygle>
cyrozap: there's also an or reduction operator
<awygle>
|bits to or all the bits of bits
<cyrozap>
Can I do that like `|(bits & mask)`?
<awygle>
cyrozap: Try It And See ^_^ (yeah i think so)
<pointfree>
cyrozap: The register/bit mapping diagram doesn't tell the whole story. It tells the story of the switch locations on the grid and their associated register bits but not the story of how they can be connected.
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<cyrozap>
awygle: For a 1-bit signal, soes it matter if I do !signal or ~signal to invert it?
<cyrozap>
*does
<awygle>
cyrozap: i don't _think_ so. i usually do ~ and a coworker does ! so i think it's fine
<cyrozap>
Ok, cool.
<cyrozap>
Modeled the PLD!
<cyrozap>
I would post the graph, but it's way too big to see any details.
<cyrozap>
Anyone know if there's a way to get yosys to output the post-generate (I'm using generate statements), pre-synth Verilog?
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<rqou>
(out of the loop): can someone explain to me exactly how blockchain kitties are breaking the network or something?
<plaes>
number of transactions ballooned?
<rqou>
that's it?
<plaes>
yeah, lack of scalability
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<rqou>
that's pretty dumb
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<azonenberg_work>
rqou: lol i heard about that
<azonenberg_work>
Basically all proof-of-work cryptocurrencies are grossly inefficient
<azonenberg_work>
and when you actually try to use it heavily, by say putting cats on it
<azonenberg_work>
it collapses
<azonenberg_work>
I have no idea whether an alternative scheme, possibly using a blockchain or possibly an entirely new architecture that hasn't yet been invented, will turn out to be better
<azonenberg_work>
But I think that PoW is going to reach scaling limits and collapse eventually
<azonenberg_work>
it's just too wasteful to catch on at a large scale
<cr1901_modern>
It's not gonna matter that regular currency is shit if we're not around to spend the new currencies
<azonenberg_work>
Lol
<azonenberg_work>
I saw some graph a while ago comparing the kWh/transaction for BTC vs MasterCard
<azonenberg_work>
it was OOMs less efficient
<cr1901_modern>
about 5000 times less efficient
<azonenberg_work>
i dont remember the number but yeah that sounds plausible
<azonenberg_work>
it was multiple ooms
<cr1901_modern>
If bitcoin transactions today were still done as they were on CPUs in 2009 (when the currency was invented) >>
<cr1901_modern>
it would exceed the amount of energy we produce on the planet
<azonenberg_work>
lolol
<azonenberg_work>
Has the "green" movement caught onto this yet?
<azonenberg_work>
Are they up in arms over cryptocurrencies?
<cr1901_modern>
Starting to
<azonenberg_work>
The BTC network alone exceeds the power consumption of some smaller countries
<azonenberg_work>
I think even some of the larger altcoins like ETH
<cr1901_modern>
azonenberg: Well, on one hand it's very damn impressive we've made efficient ASICs for bitcoin so the power consumption _only_ exceeds that of small countries, not the entire planet
<azonenberg_work>
lolol
<cr1901_modern>
On the other hand- ya know what, screw that. Efficient ASICs for bitcoin are not a positive.
<azonenberg_work>
Yes but no matter how much gold you sputter onto a turd
<azonenberg_work>
It's still a chunk of poop
<azonenberg_work>
Go find something better
<azonenberg_work>
Proof of work needs to die, and whether that's the end of cryptocurrency or simply a nudge to something better i cant say
<azonenberg_work>
But it's an environmental disaster
<cr1901_modern>
Maybe it's b/c I live in the US but I've not had any problem receiving money internationally
<cr1901_modern>
agreed
<qu1j0t3>
+1
<cr1901_modern>
I have considered accepting bitcoin for the sole purpose of converting it to $$ I can actually use, but... no. I really want no part of it :/
<azonenberg_work>
yeah proof of space is bad too, it just wastes hdd
<azonenberg_work>
instead of power
<azonenberg_work>
so now you have physical garbage piling up as your disks go obsolete b/c they arent big enough to store whatever data you need t omine
<azonenberg_work>
hardly an improvement :p
<azonenberg_work>
Air pollution or e-waste, take your pick
<cr1901_modern>
So more seriously, we're not gonna stop global warming, so we might as well live our lives as to maximize happiness while minimizing the suffering of others. Until suffering is all that is left.
<pointfree>
I prefer Norman Hardy's Digital Silk Road: http://www.cap-lore.com/Economics/DSR/ (DSR is not a currency like Bitcoin which strives to store value; DSR is a protocol to move value with only network latency.)
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<qu1j0t3>
azonenberg_work: proof of work is massive driver of e-waste _too_
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<azonenberg_work1>
qu1j0t3: Yeah i guess all those asics get thrown out when they go obsolete too
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<whitequark>
azonenberg_work: you do know bitcoin only exists at the scale it does now because of chinese subsidized hydro power?
<whitequark>
so it *might* be an environmental disaster, but not one it's *responsible* for, and certainly little to do with global warming?
<qu1j0t3>
do you have a breakdown for bitcoin use inside china vs outside china?
<whitequark>
the supermajority of mining pools are PRC citizen owned and operated
<whitequark>
because bitcoin is mostly a money laundering scheme for PRC oligarchs
<whitequark>
it's just patently idiotic to assume that bitcoin's energy source must come from fossil fuel
<qu1j0t3>
the word oligarch doesn't appear in that article
<qu1j0t3>
i was more interested in that part
<whitequark>
you do all know it's barely the only energy-intensive industry, right? like there's aluminium smelting and such
<whitequark>
which has used hydropower since forever
<awygle>
There's a possible substitution argument that the energy would be put to other uses if not used for mining. Don't know how that market actually works though.
<qu1j0t3>
smelting is actually useful
<awygle>
I was surprised nobody mentioned proof of stake? Isn't that the new hotness way to use less energy?
<whitequark>
qu1j0t3: international money transfer is actually useful
<qu1j0t3>
not that way :
<whitequark>
try dealing with AML/KYC bullshit sometime and you'll learn
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<whitequark>
anyway
* qu1j0t3
has frequently done intl money transfers, isn't sure of the issue
<qu1j0t3>
in any case, we're smart enough to come up with a better way aren't we?
<whitequark>
qu1j0t3: and where do you live?
<qu1j0t3>
in a country
<whitequark>
which country?
<qu1j0t3>
not relevant
<whitequark>
is relevant.
<whitequark>
I couldn't even get a *bank account* in HK for a year or so because of some bullshit or the other (I suspect but cannot prove that HSBC doesn't like my nationality)
<whitequark>
so fuck off with this first-world bullshit
<qu1j0t3>
if the answer is bitcoin, there's a problem with the question, sorry
<whitequark>
I don't care
<whitequark>
do something better if you do
<awygle>
whitequark: does the price of bitcoin affect its use for international money transfer? Or do you just use smaller denominations?
<whitequark>
awygle: the latter
<whitequark>
I've usedit for transferssince before it was $100 and now it's $12k and it hasn't affected me at all
<whitequark>
I've probably got a free $100 here or there because of the rise in value but it was purely coincidental
<whitequark>
and I never expected to or counted on it
<whitequark>
I think bitcoin is shit and I would be the first to switch to a PoS currency if it was viable btw
<whitequark>
most technical things and almost every social thing around bitcoin is godawful
<whitequark>
I loathe it, I just loathe the international bank system far more
<awygle>
Will the inevitable anti fraud and anti money laundering efforts ruin it for your use?
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<balrog>
whitequark: aren't the high transaction fees a problem?
<azonenberg_work>
Its choking on every netlist i've fed it
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<balrog>
azonenberg_work: did yosys netlist format change appreciably in the past yeart?
<azonenberg_work>
balrog: i dont think so but there may be new features added?
<azonenberg_work>
i've tried a couple things and it keeps dying with null derefs
<azonenberg_work>
but on different parts of the code with each netlist
<azonenberg_work>
i think it just doesnt handle my netlists well
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<cyrozap>
It's always amused me how salty some people get about Bitcoin, like it had killed their parents or something :P
<cyrozap>
Also rqou your fpgacraft server is flapping.
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<balrog>
cyrozap: it does waste electricity!
<cyrozap>
balrog: How so?
<balrog>
compute how many Wh are used by the network and consequently for each transaction
<balrog>
it's astronomically high
<whitequark>
awygle: not really. there are already such efforts underway. they proceed in parallel with what I need.
<qu1j0t3>
cyrozap: you.. aren't aware of that increasing impact?
<cyrozap>
Bitcoin does use a lot of energy, yes, but I'm still confused as to how any energy is wasted.
<whitequark>
balrog: yes, they are
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<cr1901_modern>
It's a pity to stop global warming we're gonna have to give up important modern conveniences such as airplanes and concrete
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<awygle>
I basically assume we'll solve it with large scale geoengineering
<cr1901_modern>
I don't think we'll solve it at all. But I'd genuinely rather be dead than go back to pre-modern conveniences, so...
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<cr1901_modern>
cyrozap: but I'm still confused as to how any energy is wasted <-- Personally I would rather use the electrons/holes that power hash calculation for bitcoin for something
<cr1901_modern>
that more directly benefits the human race/progress, such as BOINC attempts to do w/ idle cycles on your CPU
<awygle>
I can't say whether I'd rather be dead than those things because I can't conceive of my own death in any truly meaningful way *shrug*
<whitequark>
cr1901_modern: that makes no sense
<whitequark>
completely different people run bitcoin mining ASICs than those who run BOINC
<whitequark>
and they are powered by different electricity sources
<cr1901_modern>
It was simply an example of how I'd rather electricity would _be_ used compared to bitcoin. Bitcoin could very well indirectly fund research related to the stuff BOINC does
<cr1901_modern>
oh...
<cr1901_modern>
I mean I guess the source is relevant in the short term until we figure out how to eliminate carbon footprint...
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<rqou>
goddammit, is freenode getting a ddos again?
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<rqou>
also, azonenberg_work, starshipraider should have a qspi emulator, because reasons :P