<mithro> awygle: I may have had to rewrite history, so you should probably reclone
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<rqou> awygle: can you remind me what you're working on re: vpr?
<awygle> rqou: I'm trying to use vpack as the packer for the parallel placer project
<awygle> So I don't have to bother to write one (yet?)
<awygle> So I'm currently trying to go from the VPR xml format for packed netlist to Yosys json
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<nabla> Hi
<rqou> hi
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<rqou> azonenberg_work you're up early
<azonenberg_work> I'm on EST
<azonenberg_work> So its 0830 here
<azonenberg_work> (yay traveL)
<rqou> ah
<rqou> family?
<azonenberg_work> Yeah
<rqou> should have come to 34c3 instead :P
<azonenberg_work> lol no way
<azonenberg_work> last thing i needed is another european trip when i need to get work done
<rqou> azonenberg_work: is my otr broken btw? my laptop doesn't have the same key
<mithro> rqou: So, you getting anywhere with the symbiflow-arch-defs repo?
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<tnt> Any iCE40 expert here ? The PLL core have a SDI/SDO/SCLK pins that appanrently allow to reconfigure it at runtime but I can't find any doc about that other than a brief mention in the UltraPlus datasheet ...
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<daveshah> There's no documentation on them
<daveshah> I haven't used them
<daveshah> But they are simulated in Lattice's verilog model
<daveshah> So you could probably look at that
<daveshah> Am meaning to document them at some point
<pointfree> tnt: Vincent Jordan thinks the iCE40 cannot support dynamic live reconfiguration https://vjordan.info/log/fpga/i-am-on-reddit-woo-hoo.html It would be really cool to see that conclusion overturned.
<daveshah> I think the PLL may be an exception, because of the metioned SDI/SDO/SCK pins exposed to the fabric
<daveshah> You might need to set TEST_MODE to 1
<rqou> tnt: are you at 34c3?
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<tnt> rqou: I am
<rqou> you should just come to the openfpga assembly
<tnt> rqou: I know where it is :) Are you the UK guy who did the UltraPlus support by any chance ?
<rqou> no, but he is right next to me :P
<tnt> rqou: :) Ok, well, I'm on my way :p
<daveshah> That's me!
<daveshah> See you in a minute!
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<tnt> daveshah: interesting that according to that simulation model, it also has a 'divide-by-5' mode for HDMI ( 00-->Divide by 4, 01-->Divide by 7 , 10 --> invalid , 11 --> Divide by 5 (HDMI) )
<daveshah> Yes, that's a whole other interesting topic
<daveshah> Basically as far as my archaeology goes, there is an unreleased iCE40 device
<daveshah> Probably called the iCE40MX16K/iCE40MX8K
<daveshah> That had HDMI capable IO with a serdes, and also CSI-2
<daveshah> I don't know if that HDMI mode will work in other iCE40 devices
<daveshah> No, I think they use MachXO (probably MachXO3) fabric
<daveshah> I think the iCE40 devices with HDMI/CSI were abandonned when Lattice bought SiliconBlue
<tnt> ok
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